Showing papers on "Programmable logic device published in 1993"

Programmable logic array integrated circuits

Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

Contemporary Logic Design

Abstract: From the Publisher: The book provides comprehensive coverage of programmable logic, including ROMs, PALs, and PLAs. A Practical Matters section concludes most chapters, which ties theory to practice and explains design technologies in detail. To synthesize the text coverage of combinational and sequential design methods, the author uses a detailed case study of a simple processor design in the final two chapters. The text introduces readers to a wide range of software tools, including schematic capture, logic simulation and Boolean minimization, and demonstrates how they fit into the hardware design process. The author also encourages hands-on experimentation with software tools such as LogicWorks to bolster the reader's understanding of practical design methods.

Video processing module using a second programmable logic device which reconfigures a first programmable logic device for data transformation

Abstract: A video processing module designed for high performance using economical components. A programmable logic device (PLD) is configured to modify a data stream, in particular a video stream. The PLD can be connected to a memory resource. In addition, the PLD can be connected to a second PLD through an interruptable connection. The second PLD can be optimized for bus interface communication and connected to an external system, typically a host computer. The second PLD can take commands from the host to prepare a processing configuration for the first PLD and can connect when needed to download a configuration to the first PLD through the interruptable connection. An array of these modules can be connected in a systolic array to provide powerful, pipelined video processing.

Programmable logic device having multiplexers and demultiplexers randomly connected to global conductors for interconnections between logic elements

Abstract: A programmable logic device is provided that has a two-dimensional array of logic array blocks. The logic array blocks, which contain advanced macrocells, contain programmable input arrays based on pterm logic and are two-dimensionally interconnected with global horizontal and vertical conductors. The logic array blocks and the connections between conductors are configured using programmable multiplexers and demultiplexers. Redundant conductive pathways are provided so that the programmable logic device may be efficiently programmed to perform a variety of logic functions. Furthermore, logic is provided with each logic array block that allows the global horizontal and vertical conductors to be interconnected without directly involving the logic in the logic array block, which therefore can be used to provide greater logical functionality.

Programmable logic array integrated circuit with cascade connections between logic modules

Abstract: A programmable logic array integrated circuit has a number of relatively simple logic modules which can be interconnected in any of a wide variety of ways via a general purpose interconnection network to enable the circuit to perform logic functions which can be quite complex. In addition, at least some of the logic modules are connectable to one another by cascade connections and include additional logic elements for logically combining the outputs of the cascade connected modules so that modules can be concatenated to perform relatively complex logic functions without always having to make use of the general purpose interconnection network.

EVOLVABLE HARDWARE Genetic Programming of a Darwin Machine

Abstract: For the past three years, the author has been dreaming of the possibility of building machines which are capable of evolution, called “Darwin Machines”. As a result of several brain storming sessions with some colleagues in electrical engineering, the author now realizes that hardware devices are on the market today, which use “software configurable hardware” technologies that the author believes can be used to build Darwin Machines within a year or two. This paper suggests there are at least two approaches to be taken. The first approach uses “software configurable hardware” chips, e.g. FPGAs (Field Programmable Gate Arrays), HDPLDs (High Density Programmable Logic Devices), or possibly a new generation of chips based on the ideas that FPGAs etc embody. The second approach uses a special hardware device called a “hardware accelerator” which accelerates the simulation in software of digital hardware devices containing up to several hundred thousand gates. Darwin Machines will be essential if artificial nervous systems are to be evolved for biots (i.e. biological robots) which consist of thousands of evolved neural network modules (called GenNets). The evolution time of 1000-GenNet biots will need to be reduced by many orders of magnitude if they are to be built at all. It is for this reason that Darwin Machines may prove to be a breakthrough in biotic design. When molecular scale technologies come on line in the late 1990s, the Darwin Machine approach will probably be the only way to build self assembling, self testing molecular scale devices.

High-density erasable programmable logic device architecture using multiplexer interconnections

Abstract: A programmable logic device is presented comprising a global interconnect array whose lines are fed via programmable multiplexers to logic array blocks. The global interconnect array lines are fed to the multiplexers in a specific pattern which maximizes the user's ability to route a selected line to the output of a selected multiplexer, while at the same time maintaining higher speed and lower power consumption, and using less chip array than prior art programmable logic devices using programmable interconnect arrays based on erasable programmable read-only memories.

Multiprocessor system with cascaded modules combining processors through a programmable logic cell array

Abstract: In a multiprocessor data processing system, modules are cascaded by means of intermodule buses. Each module comprises a data processing unit, a first memory, a logic cell array programmable into four input/output interfaces, a second memory and a specialized processing unit such as a digital signal processor (DSP). A first interface, the first memory and the data processing unit are interconnected by a module bus. A fourth interface, the second memory and the specialized processing unit are interconnected by another module bus. A feedback bus connects the second and third interfaces in the last and first modules for constituting a ring. Such a system is particularly intended for image recognition, such as digitalized handwritten digits for postal distribution.

Pld connector for module having configuration of either first PLD or second PLD and reconfigurable bus for communication of two different bus protocols

Abstract: A module for supporting and connecting programmable logic devices through a common interface. A card in the PC Card format is provided with bus interface support for interconnection to other such modules. The module supports one or more programmable logic devices, each of which is connectable to four connectors, two each on top of the module, two each on the bottom of the module. Each connector includes a plurality of pins for electrical signals. These signals include one or more progammable buses, structured to form an expansible system. In a preferred embodiment, the buses include multiple, distinct, programmable buses.

Implementation of redundancy on a programmable logic device

Abstract: An improved architecture and method of operation for providing redundancy in programmable logic devices. Spare columns or rows of logic blocks 115 and switch boxes 140 are employed to replace columns or rows of logic blocks containing one or more defective logic blocks. Associated logic enable the device to bypass a column or row of logic blocks 115 containing one or more defective logic blocks 115 and to switch in a spare column or row of defect-free logic blocks 115 as replacement.

A reprogrammable gate array and applications

Abstract: A field-programmable gate array (FPGA) can implement thousands of gates of logic, has no up-front fixed costs, and can be programmed in a few minutes by writing into on-chip static memory is described. This kind of FPGA can be reprogrammed any number of times, providing a versatile platform for rapid hardware implementation. Reprogrammable technology allows software-like design methodologies to be applied to logic design. The construction of this kind of FPGA, design tradeoffs, and examples of applications that take advantage of reprogrammability are examined. >

Logic structure and circuit for fast carry

Abstract: Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the carry function. When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The invention takes advantage of the fact that a carry signal to be added to two bits can be propagated to the next more significant bit when the two binary bits to be added are unequal, and that one of the bits can serve as the carry signal when the bits are equal.

Virtual processor module including a reconfigurable programmable matrix

Abstract: A virtual processor has a reconfigurable, programmable logic matrix array for processing data in accord with a hardware encoded algorithm, a memory for storing a plurality of hardware configuration files for the programmable logic matrix array, each configuration file for programming an algorithm to be executed by the matrix array, an input/output bus for supplying data to the matrix array for processing and for obtaining processed data from the matrix array, a memory device for storing data, a VPM controller for controlling the overall operation of the virtual processor including providing operation sequence maps, providing parameters for specific operations, and providing status information, a data bus controller for controlling the data flow to the matrix array for processing, and a configuration controller for controlling the sequence of reconfiguration of the matrix array to process data by a specific sequence of algorithms.

Spyder: a reconfigurable VLIW processor using FPGAs

Abstract: A processor with multiple reconfigurable execution units has been designed and implemented. The reconfigurable execution units are implemented using reprogrammable field programmable gate array (FPGA) chips. The architecture and implementation of this processor are described in detail. An example shows that this reconfigurable processor is able to compute the new state of 100'000'000 cells of Conway's game of life per second with a clock speed of 6.25 MHz. >

Distributed-intelligence computer system including remotely reconfigurable, telephone-type user terminal

Abstract: An improved user terminal specifically designed for use in the home for accessing a wide variety of service computers is disclosed. The terminal comprises a single board computer including a microprocessor remotely reconfigurable programmable gate array logic, several types of solid-state memory, and various input-output units. The programmable gate array forms the logical connection between the microprocessor, the memory, and the input-output elements, and allows the computer to functionally mimic an IBM Personal Computer, thus allowing it to run a wide variety of software. The programmable gate array can be remotely reconfigured, and a so-called FLASH-EPROM memory is used to store reconfiguration code. This allows the hardware to be reconfigured remotely in order to add additionally function, or to cure a particular problem such as to prevent a "virus" or the like from attacking the system.

Method and apparatus for fail-safe control of at least one electro-mechanical or electro-hydraulic component

Abstract: A fault management apparatus and method are described for a system that includes at least one electro-mechanical or electro-hydraulic component, such as a system valve or main discharge pump in a process plant or water transmission line. An actuator is electrically coupled to the component for application of control signals to selectively actuate or de-actuate the component. A standby power supply, in the form of a uninterruptible power supply (UPS) stores sufficient electrical energy to energize the valve and/or the discharge pump to change the states thereof from one operational state to another. The UPS has sufficient electrical capacity to close a system valve to its fail-safe condition. The actuator can be actuated in a number of different ways, including sensing of failure of main power, manual activation or sensing of some emergency condition. Logic circuit, which may be in the form of relay or other logic, and preferably a programmable logic circuit (PLC) is used and programmed to sense the external conditions which require shutdown of the system, in which case the energy stored in the standby power supply is applied to the actuator and the component. The PLC is advantageously programmed to shutdown the system, when necessary, in accordance with a timed sequence, checking or monitoring a system at each step of the sequence as to the continued existence of the condition which required shutdown. Similarly, when the system is automatically returned on line, the PLC is advantageously programmed to check the system along each step of the sequence to insure that all of the conditions are acceptable for return of the system to the on-line condition.

Implementation of a selected instruction set cpu in programmable hardware

Abstract: A method and resulting system of designing a CPU for implementation in a configurable hardware device by identifying a series of operations in a logic scheme which are suitable for implementation in the device, identifying an executable function and any needed parameters in the logic scheme, identifying the logic flow in the scheme, providing for at least two connected system resources to implement the logic scheme, selecting an op code, and providing a way to implement the various components needed to call and execute the function according to the logic scheme A useful op code may invoke a system resource, implement the logic scheme, pass a parameter to the function, or invoke the function The configurable hardware system can function as a CPU, using logic resources including a next address RAM (20), one or more registers (60), a function execution controller (30), and one or more busses (eg 70, 80) for passing signals and data between the components and functions

Multiple-valued logic design tools

Abstract: A brief overview of past progress in multiple-valued logic design is presented. The methods are considered with respect to the likely development of multiple-valued field programmable gate arrays. Look-up table based arrays are considered in some detail and an algorithm for mapping multiple-valued functions to such an array is presented. This algorithm uses reduced order multiple-valued decision diagrams, an extension of R.E. Bryant's (1986) well-studied structure for binary functions. The algorithm works in the functional domain and does not require the synthesis and optimization of a conventional network prior to technology mapping. >

Introduction to Digital Logic Design

Abstract: From the Publisher: John P. Hayes, a well-known authority in the area of computer engineering, now brings his expertise to digital logic design. Intended as a mainstream introduction for the first course, Introduction to Digital Logic Design provides a presentation which is both scholarly and highly supportive of student learning. In addition, it presents the traditional core topics including sequential and combinational design and register level logic. This is the first introductory text that provides balanced coverage of concepts, techniques and practice. Also, the text includes excellent coverage of the most modern topics and technologies -- programmable logic devices (PLD's), the testability, and computer aided design (CAD). This text has an attractive, practical design that highlights a number of features that support student learning.

Architectural tradeoffs in field-programmable-device-based computing systems

Abstract: Reprogrammable Field-Programmable Gate Arrays (FPGAs) have enabled the realization of high-performance and affordable reconfigurable computing engines. The authors examine the architectural tradeoffs involved in designing general purpose FPGA-based computing systems with field-programmable gate arrays and field-programmable interconnects. The fact that FPGAs provide both programmable logic and programmable interconnects raises numerous design issues that need to be considered with care. Factors that influence the tradeoffs are routability, rearrangeability and speed. >

Ram convertible look-up table based macrocell for PLDs

Abstract: A macrocell for use in programmable logic devices (PLDs) that provides for standard memory functions with minimum overhead circuitry. In a PLD that uses static random access memory (SRAM) as its configuration host, the circuit of the present invention enables the SRAM to be programmed via bidirectional look-up tables. In a user mode, macrocell bidirectional look-up table implements the configured logic, while in supervisor and memory modes the look-up table acts as an address decoder for the SRAM. A tristate buffer and two pass gates to direct data out of, and drive data into, the SRAM cells through the look-up table are the only additional circuitry required.

On Routability Prediction for Field-Programmable Gate Arrays

Abstract: Efficient utilization of Field Programmable Gate Arrays (FPGAs) depends on the ability to determine whether designs will exceed the logic or routing capacities of the devices. Here, we focus on the problem of assessing the routability of designs for FPGAs before place-and-route. Specifically, we identify the relevant wireability theories, modify and adapt the theories for FPGAs, and conduct experiments to validate the theories.

PLD with selective inputs from local and global conductors

Abstract: A programmable logic device is presented comprising a global interconnect array whose lines are fed via programmable multiplexers to two stacks of logic array blocks on its sides. The logic array blocks include CMOS look up table based logic modules that consume zero DC power. The global interconnect array lines are fed to the multiplexers in a specific pattern which maximizes routing flexibility and speed. The combination of low power logic array blocks and high performance global interconnect array allows for increased logic density at lower power consumption compared to prior art programmable logic array devices.

A self-reconfiguring processor

Abstract: Recent developments in the design and fabrication of field programmable logic devices (FPGA ’s) may well change the way in which we design and fabricate conventional microprocessors. The use of uncommitted logic whose function may be modified at run tame makes the prospect of dynamic application specific integrated circuits closer to reality than ever before. Much of the work to date on reconfigurable logic has focussed on its application in co-processor and “glue ’’ roles. This paper discusses how complete processors might be fabricated with a minimum of “fixed” or static logic. It is shown that an order to exploit FPGAs, a processor that as radically different from conventional architectures is required. The paper concludes by considering what evolutions of current logic families would favour this type of application.

Synthesis methods for field programmable gate arrays

Abstract: Field programmable gate arrays (FPGA ’s) reduce the turnaround time of application-spec@c integrated circuits from weeks to minutes. However, the high complexity of their architectures makes manual mapping of designs time consuming and error prone thereby offsetting any turnaround advantage. Consequently, effective design automation tools are needed to reduce design time. Among the most important is logic synthesis. While standard synthesis techniques could be used for FPGA’s, the quality of the synthesized designs is often unacceptable. As a result, much recent work has been devoted to developing logic synthesis tools targeted to different FPGA architectures. The paper surveys this work. The three most popular types of FPGA architectures are considered, namely those using logic blocks based on lookuptables, multiplexers and wide AND/OR arrays. The emphasis is on tools which attempt to minimize the area of the combinational logic part of a design since little work has been done on optimizing performance or routability, or on synthesis of the sequential part of a design. The different tools surveyed are compared using a suite of benchmark designs.

Methods and apparatus for programming cellular programmable logic integrated circuits

Abstract: In order to simplify the programming structure and facilitate testing of that structure, the programmable elements in a cellular programmable logic integrated circuit (such as a field programmable gate array ("FPGA") or a programmable logic device ("PLD")) are connected in one or more series with switches interposed between the elements in the series. Initially, all of the switches in each series are enabled so that the ability of the series to correctly pass data can be tested. Thereafter, the switches are progressively disabled, starting from the switch which is most remote from the data source, so that data is stored in successive programmable elements, again starting with the programmable element which is most remote from the data source.

Arrangement for parallel programming of in-system programmable ic logic devices

Abstract: A plurality of programmable logic devices (1-6) are connected in parallel to a programming command generator (10). A device selector (11) connects individual devices (1-6) with the programming command generator (10), thereby permitting the individual devices to be programmed without routing the programming data through other devices. In an alternative embodiment, an identification code is used to place the individual device in a condition to receive programming data. Using the teachings of this invention, programming data may initially be entered into a plurality of devices, and then the data entered in all the devices may be used to program the devices simultaneously. This procedure requires less time than entering data and giving each device the execute command in sequence.

Programmable function unit with programmable fast ripple logic

Abstract: A programmable function unit (PFU) well adapted for use in a field programmable gate array (FPGA) is disclosed. The PFU utilizes programmable fast ripple logic. A programmable generator and/or a programmable propagator are implemented in look up tables in each PFU block. A multiplexer under control of the propagator determines whether to transmit the carry in from the previous block or to transmit the generator signal.

One time programmable fully-testable programmable logic device with zero power and anti-fuse cell architecture

Abstract: There is a zero power programmable logic device with a one time programmable and fully-testable anti-fuse cell architecture. Specifically, a half-latch and fuse cell circuit allows the PLD to use "zero power" during the standby period since the sense amps are not used to maintain the programmed logic. Additionally, the PLD is capable of being tested for logic gate and logic path integrity, and anti-fuse electrical parameters without permanently programming the anti-fuse.

Macrocell comprised of two look-up tables and two flip-flops

Abstract: A macrocell for use in a programmable logic device (PLD) providing for enhanced logic capability and reduced setup time. The preferred embodiment of the macrocell includes two look-up tables, for increased fan-in, and two flip-flops that increase fan-out, thereby doubling logic capability of the PLD without unacceptably increasing device size. Doubling the register count makes this PLD particularly suitable for applications employing high density sequential logic. Furthermore, a second register can be used for receiving fast input signals form an input to the PLD to reduce setup time.