Showing papers on "Registered memory published in 1975"

Memory control system for transferring selected words in a multiple memory word exchange during one memory cycle

Abstract: A memory control apparatus for use in a digital computer system. The computer system comprises a central processing unit and a main memory which has a plurality of memory units. The processor has control circuitry for simultaneously addressing a plurality of words stored in the memory locations in the memory units. The processor addresses the plurality of words by the combination of a memory address signal and word request control signal which are equal to the number of words to be transferred. While addressing of the memory units occurs in parallel, the transfer of words occurs serially. The initial word as defined by the memory address signal is transferred first with the remaining words transferred in ascending modulo four order. If one or more of the four words has not been requested, it is automatically skipped by the control apparatus with no loss in time or continuity. Logic in both the processor and the memory unit is initialized to acount for the words being transferred such that each word selected is stored in the proper buffer.

Erasable programmable read-only memory

Abstract: A TTL compatible erasable programmable read-only memory (PROM) which uses a single n-channel device having a floating gate for each memory cell. The entire memory including the periphery circuits, are disposed on a silicon substrate. Only a single externally generated high voltage input or "pin" is required for programming.

Charge coupled device memory system with burst mode

Abstract: A circular shift register memory system comprising L sections each having K circular charge storage shift registers of N bits each for storing blocks of N, K-bit words and accessing the words or blocks thereof in parallel. The L memory sections are refreshed by N-bit clock bursts which are successively and periodically applied to the memory sections by a refresh counter, decoder and gating logic. A read/write decoder decodes memory section addresses and controls the application of N-bit clock bursts to the particular addressed memory sections for access purposes. In a random access mode, word access is facilitated by counters which count the number of read/write or refresh clock pulses for comparison to a word address. A memory section comparator prevents interference between access and refresh operations by inhibiting the refresh circuitry if the refresh counter directs refresh of a memory section undergoing access and by inhibiting the read/write circuitry in certain cases where access is requested to a memory section undergoing refresh.

Method and means to access and extended memory unit

Abstract: Access to additional memory is provided by extending two registers and adg a no-index register reference which creates an extended data address register for directly addressing the additional memory.

Fail soft memory

Abstract: A firmware/hardware mechanism in a general purpose computer system automatically provides alternate addressing paths for addressing data in the same or another main memory module when a failure is detected in a portion of the main memory or main memory module. Two types of memory failures are detected and an alternate path provided for each type of failure. The first type is a failure in a memory which is not detected by memory hardware or systen interface unit SIU hardware; such failure is handled by an exception processing mechanism to provide an alternate path to a good memory module. The second type of failure is detected by memory hardware or systen interface unit SIU hardware; such failure is handled by an interrupt processing mechanism to provide an alternate path to a good memory module.

User variable computer memory module

Abstract: A memory module containing addressable memory devices, and the circuits necessary to address and drive these devices, is configured so that a trade-off between memory size and word length can be made by rewiring the backplane. Thus, a single memory module design can be used for a variety of computer memory applications. This is accomplished by incorporating on the module a complete set of addressing and signal driving circuits, and allowing for the control of these module components through a system of control lines wired through the backplane.

Dynamic memory initializing apparatus

Abstract: Initializing apparatus for a dynamic memory causes data to be written into a different cell of each array of the memory during each refresh cycle until all the memory cells of the arrays have data written into them. The memory initializing apparatus then ceases causing data to be written into the array during subsequent refresh cycles.

Variable module memory

Abstract: A variable module memory, particularly suitable for use in a programmable controller, includes a set of up-to-N memory modules each for storing a plurality of words of n bits. N receptacle means are provided for receiving the set of memory modules and for coupling the received memory modules to a common serial bus. Control means is provided, coupled via said receptacle means, to said up-to-N memory modules for providing address signals for selectively addressing the words of a selected memory module to provide the contents stored therein serially to said common serial bus. A pull-up resistor connecting a predetermined voltage to a common serial bus detects the absence of memory modules in the receptacles and forces the serial bus to a predetermined binary state for all bits or all words for a vacant receptacle means.

Anaysis of interleaved memory systems using blockage buffers

Abstract: A model of interleaved memory systems is presented, and the analysis of the model by Monte Carlo simulation is discussed. The simulations investigate the performance of various system structures, i.e. schemes for sending instruction and data requests to the memory system. Performance is measured by determining the distribution of the number of memory modules in operation during a memory cycle.An important observation from these investigations is that separately grouping instruction and data requests for memory can substantially increase the average number of memory modules in operation during a memory cycle. Results of the simulations and an analytical study are displayed for various system structures.

Access control unit

Abstract: An access control unit for controlling a memory device having a plurality of memory units for storing data in a manner whereby the memory units are accessed sequentially, comprises a data register for storing data read out from the memory device, a cycle designation device for indicating in every cycle the memory unit of the memory device to be accessed in the relevant cycle, an address device for providing in each cycle an address to the memory unit indicated by the cycle designation device, a non-coincidence detection circuit for detecting non-coincidence between the memory unit indicated by the address and the memory unit practically provided with that address, and an invalidating device utilizing the output of the non-coincidence detection circuit for invalidating data read out from the memory device in a cycle a specified number of cycles after that in which non-coincidence is detected.

The cost and performance tradeoffs of buffered memories

Abstract: An analysis of the performance enhancement achieved and the incremental costs accrued in buffering (using a cache memory) memory systems is made. Buffering is found to be cost-effective even for minicomputer memories. The study indicates that the flagged registered swap algorithm is superior to three other common algorithms used. It is shown that when jobs are switched, a substantial number of memory requests are required before the buffer fills and gives a high hit ratio. It is also shown that individuaIly buffered main-memory modules can be interleaved to achieve very high system performance.

Universal first-in first-out memory device

Abstract: A universal first-in first-out memory device is provided on a single semiconductor chip, which device may constitute a building block for digital systems. Provisions have been made in the device of this invention, as a result of unique circuit designs, to enable expansion of one memory device into an array of several memory devices to thereby expand the number of binary digits that can be stored, or the amount of data that can be stored in the array.

Memory with error detection and correction means

Abstract: The invention relates to a memory device which initially consists of a number of modules which can be exchanged and wherein no non-correctable storage errors are present. If such errors occur at a later stage, the address of the detective module is applied to an inversion device which is connected between an address input line and the actual memory device. This address actuates the inversion device such that the relevant memory unit becomes the last one in the sequence of memory units. By blocking the highest address, a memory device having a substantially unchanged capacity can thus be automatically realized. By replacement of the defective module at a later stage, the original capacity can be restored. If a second module fails after the first module has become defective, the sequence can be modified again etc., with the result that each time an as large as possible number of modules of the memory device can be addressed in a consecutive sequence.

Data display system designed as a microcontroller

Abstract: A programmable read-only memory (PROM) provides a fixed stored microroutine to logic circuitry which controls the fetching of data from a memory to a variable number of video display units. The microroutine includes a small number of micro subroutines that are utilized to fetch the addresses in a separate main memory, where character data is to be found. Similarly, subroutines are provided for obtaining entry marker (cursor) addresses from the main memory. Additional subroutines are provided for indirectly addressing the main memory for the character data which undergoes encoding by a character generator that is capable of providing video information to eight channels.

Timing control means for a magnetic domain memory

Abstract: A non-volatile digital memory is utilized to generate digital pulses for controlling memory operations of a magnetic domain memory system. Each word stored in the memory contains data corresponding to the desired control signals. The digital memory synchronizes the control pulses with the in-plane rotating magnetic field. During each rotation of the magnetic field, a binary counter sequentially addresses the words stored in the digital memory such that the outputs from the digital memory correspond to the desired control signals.

Buffer memory control method

Abstract: PURPOSE: When the main memory is shared by other data processing equipment, jamming by the other processing equipment is avoided by shortening the working cycle time of the address indexing equipment than that of the buffer memory. COPYRIGHT: (C)1976,JPO&Japio

Memory drive circuit

Abstract: PURPOSE:The phenomenon of memory contents rewritten by the system power going off is prevented

Memory steering in a data processing system

Abstract: In an input/output data processing system employing local and remote memory and paged data storage, memory steering is included in the address development, thus eliminating the need for special memory configuration logic. Words used in constructing absolute memory addresses for data fetches include address portions referencing local/remote memory, specific memory, and/or lack of memory residence for effecting a system fault procedure.

Read-only memory

Abstract: A read-only memory is provided with a multiplexer unit having at least one merged column. Thus, the read-only memory occupies a greatly reduced space.

Dynamic MOS memory regeneration circuit - with regeneration effected in first part of each working cycle

Abstract: The method is for the regeneration of the content of a MOS memory, in which working cycle of the memory is is divided into a first period in which only regenerative processes occur and a second period in which only reading or writing processes occur. A MOS memory to operate on this principle consists of a set of memory cells with a decoder connected to the word lines and with reading and writing amplifiers connected to the bit lines and a clock unit under the control of a central unit. After the clock unit (37) a divider (35) is connected. A cyclic counter (34) determines the cells to be regenerated, an address register (33) stores the working addresses, and between the address register and the decoder (31) a multiplexer is inserted (32). The cyclic counter may be a shirt register. The system is particularly suitable for small memories with relatively simple dynamic cells having a low retention time.

Main memory access controller

Abstract: PURPOSE: To enable transfer of information between processor and subprocessor by means of main memory access controller (hereinafter abbreviated as MAC) in a multiple processing constituting system using a common main memory access controller. COPYRIGHT: (C)1976,JPO&Japio

A parametric associative memory emulation

Abstract: An experimental associative memory facility has been created by microprogramming a conventional computer. The microprogramming was done by expansion of an IBM 1130 emulation that was microcoded on a Digital Scientific Corporation META 4 computer. The associative memory (AM), as seen by the 1130 applications programmer, is an integral part of the computer with 54 machine instructions provided for its control and use.The structural characteristics of the apparent associative memory are parametrically defined to the emulation via a special SETUP command. This command may occur repeatedly within a program to dynamically alter the AM's characteristics or, indeed, to provide several different AM's. The characteristics that may be specified include the cell width (W) in 16-bit word increments, the number of cells (N), the locations in core memory to be used by the AM and its associated registers, and the memory protect status of these memory locations. The parameters are maintained in a fast scratch-pad memory, whence they are employed to control the AM emulation.Three pseudoregisters are used by the associative memory: (1) a data register (DR), which can hold the contents of one cell (i. e., W bits in length); (2) a response register (RR) N bits in length; and (3) an availability register (AR), also N bits in length.The data register provides the primary interface between the AM and the 1130 program. The response register is employed to indicate which cells in the AM have responded to a given search command. The availability register is used to indicate which cells are empty (or available) and which are to be considered whenever a search command is executed. The AM can be addressed either conventionally or associatively.The commands provided to utilize the AM fall into five categories: (1) register commands to manipulate the DR, RR, and AR; (2) fetch and store commands to store and retrieve information; (3) search commands to compare a given argument against the AM; (4) field-to-field search commands that compare two fields within each cell; and (5) test and branch instructions. Field specifications for search commands are defined through the use of pointer and length information contained within the command.Communication with the AM is via the DR. Search arguments and data to be stored are placed there, as are data retrieved from the AM. Searches permitted include match, no match, less than, less than or equal to, greater than, greater than or equal to, next lower, next greater, minimum, and maximum.The commands themselves, viewed as 1130 operators, may occupy either one, two, or three machine words, depending upon the operation, and may contain an address, one or two pointer specifications, one or two length specifications, a reset flag, or an immediate value, as required. Indexing is permitted for those operations having an address. The code-cracking mechanism of the 1130 emulation is used but is augmented to handle the three-word instructions. Microsubprograms are then executed for each emulated instruction or class of instructions.The META 4 computer on which the AM system was implemented is a flexible, logical processor that is controlled by an easily modified, random-access, read-only memory (ROM). Up to 32 general-purpose registers may be employed, together with three data buses (two source and one destination), an arithmetic-logical unit, and a shifter unit. Control is exercised at the gate level via microcode commands, 32 bits in length, in the ROM. Core memory is treated essentially as a peripheral with access via a pair of registers, one for data and the other for address information. The usual complement of peripherals, card readers, printers, disks, etc., may be attached.The basic hardware configuration required for 1130 emulation on a META 4 consists of 8K main-core memory, 2K read-only memory, and 20 registers. This configuration was augmented for the AM emulation by the addition of 8K more core, 2K additional ROM, two additional registers, two scratch-pad memories of 64 words each, and a set of internal timers to provide timing information on application programs.Several applications have been programmed in both a conventional manner and by using the associative memory capability in order to obtain relative timing information. One such application, a personnel file information storage and retrieval system, has provided a speed advantage of as much as 10 to 1 when the AM is employed. Building on the AM capability, a set of macroinstructions was developed to provide an apparent associative processor. Several matrix manipulation routines were developed using this facility, and these routines also exhibited a significant speed advantage over their conventionally programmed counterparts.

A design for a low-cost high-speed m.o.s. associative memory

Abstract: A design for a 128-bit m.o.s. associative memory is described. The memory array can be integrated on a 1.6 × 2.9 mm (63 × 114 mil) chip using standard silicon-gate m.o.s. fabrication technology. The basic memory cell is dynamic in operation, but external refresh circuitry is not required. Computer simulation studies predict match and read access times of 10 ns, and a write ‘toggle’ time of 25 ns. A design for a cheap interface buffer circuit is also described. With these two designs it is possible to build a low-cost associative memory array, organized as 256 words of 256 bits each, which is TTL compatible and will operate with a 100 ns cycle time.

Fast access antiphase control memory for digital data switches

Abstract: The disclosure describes a control memory for addressing inlet and outlet switching stages of a three stage digital switch. The control memory comprises two identical random access memories (RAM's) each having an address storage capacity equal to half the number of simplex connections which can be made through either stage of the switch. The arrangement described allows a large saving in the number of memory bits necessary to address the inlet and outlet switching stages and enables fast access of the control memory for the purpose of establishing or terminating connections.

Functional Description of the EMMY Main Memory System.

Abstract: : This document gives the functional description of an emulation oriented main memory system for use on the EMMY bus system. The main memory system consists of a byte addressable core memory system and a memory controller which performs elementary transformations on address and data under CPU control. (Author)