Showing papers on "Run queue published in 2003"

Non-blocking concurrent queues with direct node access by threads

Abstract: Multiple non-blocking FIFO queues are concurrently maintained using atomic compare-and-swap (CAS) operations. In accordance with the invention, each queue provides direct access to the nodes stored therein to an application or thread, so that each thread may enqueue and dequeue nodes that it may choose. The prior art merely provided access to the values stored in the node. In order to avoid anomalies, the queue is never allowed to become empty by requiring the presence of at least a dummy node in the queue. The ABA problem is solved by requiring that the next pointer of the tail node in each queue point to a “magic number” unique to the particular queue, such as the pointer to the queue head or the address of the queue head, for example. This obviates any need to maintain a separate count for each node.

Packet processing system

Abstract: Some embodiments relate to a processor to provide a plurality of execution threads, a local memory associated with the processor, and a content-addressable memory associated with the processor. An execution thread of the processor may determine an ordering queue, associate a current thread with a last position in the ordering queue, receive a queue release signal from a previous thread in the ordering queue, and execute a critical code segment associated with the ordering queue.

System and method for asymmetric heterogeneous multi-threaded operating system

Abstract: A system and method for an asymmetric heterogeneous multi-threaded operating system are presented. A processing unit (PU) provides a trusted mode environment in which an operating system executes. A heterogeneous processor environment includes a synergistic processing unit (SPU) that does not provide trusted mode capabilities. The PU operating system uses two separate and distinct schedulers which are a PU scheduler and an SPU scheduler to schedule tasks on a PU and an SPU, respectively. In one embodiment, the heterogeneous processor environment includes a plurality of SPUs. In this embodiment, the SPU scheduler may use a single SPU run queue to schedule tasks for the plurality of SPUs or, the SPU scheduler may use a plurality of run queues to schedule SPU tasks whereby each of the run queues correspond to a particular SPU.

System for preventing periodic load balancing if processor associated with lightest local run queue has benefited from idle processor load balancing within a determined time period

Abstract: An apparatus and methods for periodic load balancing in a multiple run queue system are provided. The apparatus includes a controller, memory, initial load balancing device, idle load balancing device, periodic load balancing device, and starvation load balancing device. The apparatus performs initial load balancing, idle load balancing, periodic load balancing and starvation load balancing to ensure that the workloads for the processors of the system are optimally balanced.

Apparatus and method for minimizing lock contention in a multiple processor system with multiple run queues

Abstract: Apparatus and methods are provided for selecting a thread to dispatch in a multiple processor system having a global run queue associated with each multiple processor node and having a local run queue associated with each processor. If the global run queue and the local run queue associated with the processor performing the dispatch are both not empty, then the highest priority queue is selected for dispatch, as determined by examining the queues without obtaining a lock. If one of the two queues is empty and the other queue is not empty, then the non-empty queue is selected for dispatch. If the global queue is selected for dispatch but a lock on the global queue cannot be obtained immediately, then the local queue is selected for dispatch. If both queues are empty, then an idle load balancing operation is performed. Local run queues for other processors at the same node are examining without obtaining a lock. If a candidate thread is found that satisfies a set of shift conditions, and if a lock can be obtained on both the non-local run queue and the candidate thread, then the thread is shifted for dispatch by the processor that is about to become idle.

Dynamic queue for use in threaded computing environment

Abstract: The present invention provides a dynamic queue for managing jobs n a threaded computing environment. Jobs may be placed in the queue, which may be maintained within a context of the computing environment, at a given priority level. The priority of jobs within the queue and the receipt time of each job is maintained. A job may also be placed within the queue with triggers that, if met, will result in the priority of the job being changed or will result in the job being removed from the queue entirely. Methods in accordance with the present invention also provide a method for raising an exception should multiple threads seek to access objects within a single context. Methods in accordance with the present invention also provide compatibility with prior computing systems and methodologies by providing for integration of prior static queues with dynamic queues in accordance with the present invention, and by providing methods for a given thread to be pinned to a particular context of a computing environment.

Method for determining idle processor load balancing in a multiple processors system

Abstract: An apparatus and methods for periodic load balancing in a multiple run queue system are provided. The apparatus includes a controller, memory, initial load balancing device, idle load balancing device, periodic load balancing device, and starvation load balancing device. The apparatus performs initial load balancing, idle load balancing, periodic load balancing and starvation load balancing to ensure that the workloads for the processors of the system are optimally balanced.

Buffer memory reservation

Abstract: Network applications may require a guaranteed rate of throughput, which may be accomplished by using buffer memory reservation to manage a data queue used to store incoming packets. Buffer memory reservation reserves a portion of a data queue as a dedicated queue for each flow, reserves another portion of a data queue as a shared queue, and associates a portion of the shared queue with each flow. The amount of the buffer memory reserved by the dedicated queue sizes and the shared queue portion sizes for all of the flows may exceed the amount of physical memory available to buffer incoming packets.

Method and apparatus for weighted fair queuing

Abstract: Management of a plurality of queues is made weighted and fair through the introduction of a system of credits. A credit is spent when a fixed-size unit of storage is served from a selected one of the queues. A scheduler selects a queue when an identifier of the queue reaches the head of a service queue. Credits are regained through a distinct credit management method that takes into account a weight associated with each queue. The arrival of new data in a previously empty queue can trigger the inclusion of the previously empty queue in data structures associated with the credit management method.

Asymmetric heterogeneous multi-threaded operating system

Abstract: A method for an asymmetric heterogeneous multi-threaded operating system is presented. A processing unit (PU) provides a trusted mode environment in which an operating system executes. A heterogeneous processor environment includes a synergistic processing unit (SPU) that does not provide trusted mode capabilities. The PU operating system uses two separate and distinct schedulers which are a PU scheduler and an SPU scheduler to schedule tasks on a PU and an SPU, respectively. In one embodiment, the heterogeneous processor environment includes a plurality of SPUs. In this embodiment, the SPU scheduler may use a single SPU run queue to schedule tasks for the plurality of SPUs or, the SPU scheduler may use a plurality of run queues to schedule SPU tasks whereby each of the run queues correspond to a particular SPU.

System and method for CPI scheduling on SMT processors

Abstract: A system and method for identifying compatible threads in a Simultaneous Multithreading (SMT) processor environment is provided by calculating a performance metric, such as CPI, that occurs when two threads are running on the SMT processor. The CPI that is achieved when both threads were executing on the SMT processor is determined. If the CPI that was achieved is better than the compatibility threshold, then information indicating the compatibility is recorded. When a thread is about to complete, the scheduler looks at the run queue from which the completing thread belongs to dispatch another thread. The scheduler identifies a thread that is (1) compatible with the thread that is still running on the SMT processor (i.e., the thread that is not about to complete), and (2) ready to execute. The CPI data is continually updated so that threads that are compatible with one another are continually identified.

Apparatus and method for dispatching fixed priority threads using a global run queue in a multiple run queue system

Abstract: Apparatus and methods for dispatching fixed priority threads using a global run queue in a multiple run queue system. The apparatus includes a controller, memory, initial load balancing device, idle load balancing device, periodic load balancing device, and starvation load balancing device. The apparatus performs initial load balancing, idle load balancing, periodic load balancing and starvation load balancing to ensure that the workloads for the processors of the system are optimally balanced.

Services processor having a queue operations unit and an output scheduler

Abstract: In a services processor (110), a queue operations (218) unit controls the output of processed data packets from the services processor (110). In accordance with a hybrid list/calendar queue priority scheme (200), the queue operations (218) unit uses a unique data structure comprising a tree of calendar arrays and queue lists to schedule the data packets for output.

Apparatus for minimizing lock contention in a multiple processor system with multiple run queues when determining the threads priorities

Abstract: Apparatus and methods are provided for selecting a thread to dispatch in a multiple processor system having a global run queue associated with each multiple processor node and having a local run queue associated with each processor. If the global run queue and the local run queue associated with the processor performing the dispatch are both not empty, then the highest priority queue is selected for dispatch, as determined by examining the queues without obtaining a lock. If one of the two queues is empty and the other queue is not empty, then the non-empty queue is selected for dispatch. If the global queue is selected for dispatch but a lock on the global queue cannot be obtained immediately, then the local queue is selected for dispatch. If both queues are empty, then an idle load balancing operation is performed. Local run queues for other processors at the same node are examining without obtaining a lock. If a candidate thread is found that satisfies a set of shift conditions, and if a lock can be obtained on both the non-local run queue and the candidate thread, then the thread is shifted for dispatch by the processor that is about to become idle.

Operating-system-independent modular programming method for robust just-in-time response to multiple asynchronous data streams

Abstract: An operating-system-independent modular programming method is disclosed, which includes providing one or more tasks, one or more task queues, and zero or more condition queues. Each task is a program that is run in sequence. Each task queue includes a task queue program and a queue containing zero or more tasks. Each condition queue includes a condition queue program and a queue containing zero or more tasks and associated conditions. Each task includes task ending code that refers to zero, one, or more than one successor task, and the task queue program or the condition queue program handles each such successor task by either running it or placing it in a task queue or a condition queue. The programming method further includes providing a fan and an end fan construct to enable a parent task to generate a plurality of child sequences. These program constructs may be used to form pseudothreads, each pseudothread being a single sequence of control, with interruptions allowed but no concurrency of execution, implemented in an operating system independent way. Also disclosed is an application of this programming method to accomplish robust just-in-time response to multiple asynchronous data streams in a RAID control program. The RAID control program includes a plurality of requesters, a resource allocator, and a plurality of stripe parity and IO masters, and an optional chainer, each being implemented as a pseudothread.

System, method and program tool to reset an application

Abstract: A computer program product and system for deleting objects used or managed by an application or application instance is disclosed. First program instructions identify the objects. Second program instructions write an executable program to delete the objects which were identified. There are wide variety of objects than can be deleted such as local queues, alias queues, remote queues, security objects, channel objects, process objects, etc. The first program instructions identify a queue object and determine whether the queue object contains a work item. If so, the second program instructions write into the executable program a command to clear the work item. A computer program product, system and method for deleting a queue object managed by an application or application instance is also disclosed. Channels used by other applications or other application instances to lock and access a queue defined by the queue object are identified. Then, the channels are stopped. Afterwards, the work item(s) on the queue are cleared and then the queue object is deleted.

Queues for information processing and methods thereof

Abstract: Systems and methods implement queues that perform write operations in a re-circulating sequential manner. The nature of the queue systems of the present invention allow writes to the queue to occur independently of read operations therefrom. A current event counter is updated by the queue logic to keep track of a count value that corresponds to the total number of data events written to the queue. Preferably, the current event counter is capable of counting an amount greater than the total number of addressable storage locations of the queue. A write pointer may be derived from the count value stored in the event counter from which a select addressable storage location of the queue can be determined for queuing each new data event. Read operations from the queue may be performed according to any prescribed manner, including random access thereto. Moreover, read operations can be performed in a first manner when no overflow is detected, and in a second manner in response to overflow.

Apparatus, system and method for quickly determining an oldest instruction in a non-moving instruction queue

Abstract: An apparatus, system and method for quickly determining an oldest instruction in a non-moving instruction queue of a processor are provided. Particularly, instructions are stored, one at a time at a clock cycle, in the non-moving queue. At every clock cycle, a present status of the instructions in the queue is recorded. Using the present status of the instructions in the queue in conjunction with previously recorded statuses of the instructions, the oldest instruction in the queue is determined. The status of the instructions in the queue includes whether or not the instruction has been issued for execution as well as whether or not it is known that the issued instruction has been accepted for execution.

System and method for scheduling compatible threads in a simultaneous multi-threading processor using cycle per instruction value occurred during identified time interval

Abstract: A system and method for identifying compatible threads in a Simultaneous Multithreading (SMT) processor environment is provided by calculating a performance metric, such as cycles per instruction (CPI), that occurs when two threads are running on the SMT processor. The CPI that is achieved when both threads were executing on the SMT processor is determined. If the CPI that was achieved is better than the compatibility threshold, then information indicating the compatibility is recorded. When a thread is about to complete, the scheduler looks at the run queue from which the completing thread belongs to dispatch another thread. The scheduler identifies a thread that is (1) compatible with the thread that is still running on the SMT processor (i.e., the thread that is not about to complete), and (2) ready to execute. The CPI data is continually updated so that threads that are compatible with one another are continually identified.

Method and apparatus for implementing infiniband transmit queue

Abstract: A method, apparatus and computer program product are provided for implementing a transmit queue. A queue pair context memory is provided for storing a set of pointers for each queue pair. The set of pointers are used to control the transmit queue for receiving, processing, and sending messages. Responsive to identifying an error for a queue pair, a limit pointer enable bit and a limit pointer to identify a last request for processing after the error are stored in the queue pair context memory for the queue pair.

History FIFO with bypass

Abstract: An apparatus and method for maintaining a circular FIFO (first-in, first-out) queue in an I/O (input-output) subsystem of a computer system such as a server, workstation, or storage machine. The queue is coupled to a bypass circuit, used to provide access to data items out of the order in which they were stored in the queue, thus bypassing the latency inherent in retrieving the items from the queue. Control logic maintains write and read pointers indicating locations in the queue for writing and reading data items. The write pointer is incremented upon every data event to the queue, thereby maintaining a history of data that has been written to the queue, which is useful for diagnostic purposes. A history flag is maintained to indicate whether the write pointer has wrapped around the addresses in the queue, indicating whether all data items in the queue are valid for diagnostic purposes.

System and method for queue management using queue sets

Abstract: The disclosure describes queue management based on queue sets. A queue set comprises a group of packets or packet references that are processed as a single entity or unit. For example, when a queue set reaches the head of a queue in which it is stored, the entire queue set including its packets or packet references is passed for scheduling as a single unit. A queue set provides the benefit of a single operation associated with enqueuing and a single operation associated with dequeuing. Since only one operation on a queue is required for the typical case of several packets in a queue set rather than for every packet, the rate of queue operations may be significantly reduced. A queue set has a target data unit size, for example, a roughly equal number of packet bytes represented by each queue set, regardless of the number of packets referenced by a queue set. This means that a scheduler of a queue manager, which is tasked with metering the number of packet bytes transmitted from each queue per time unit, is provided with a list of packets which represents a predictable quantity of packet bytes, and this predictability streamlines the scheduling task and significantly reduces the number of operations.

Method and apparatus for address translation pre-fetch

Abstract: An end of a queue or a page-crossing within a queue is detected. A virtual memory address for the head of the queue or for the next queue page is pre-translated into a physical memory address while the last entry in the queue or in the current queue page is being serviced.

Apparatus and method for queue assignment for each link in multi-links of an access pointer controller

Abstract: A system and method for managing traffic in a communication system assigns multiple links in a system to a queue. The queue is formed from one or multiple memories and a queue assignment unit assigns banks in the queue to one or more links. The queue assignment also writes data in the banks of specific links through a write control signal. A signal detection unit detects availability of a line interface unit, and a data control unit that reads data from the queue and writes it in the line interface unit. Through this structure, a faster and more efficient data transmission system is formed.

History FIFO with bypass wherein an order through queue is maintained irrespective of retrieval of data

Abstract: An apparatus and method for maintaining a circular FIFO (first-in, first-out) queue in an I/O (input-output) subsystem of a computer system such as a server, workstation, or storage machine. The queue is coupled to a bypass circuit, used to provide access to data items out of the order in which they were stored in the queue, thus bypassing the latency inherent in retrieving the items from the queue. Control logic maintains write and read pointers indicating locations in the queue for writing and reading data items. The write pointer is incremented upon every data event to the queue, thereby maintaining a history of data that has been written to the queue, which is useful for diagnostic purposes. A history flag is maintained to indicate whether the write pointer has wrapped around the addresses in the queue, indicating whether all data items in the queue are valid for diagnostic purposes.

Techniques for improved transaction processing

Abstract: Performance improved transaction identification queue structures and techniques for implementing such structures. Specifically, a read queue structure and a dropped queue structure are provided in a host/data controller. Once the read queue structure is filled with read requests, any read requests corresponding to transactions that can be completed without retrieving data from main memory may be moved to the dropped queue structure. The dropped queue structure may provide substitute entrypoints for storage of subsequent read requests.

Method and system for management of global queues utilizing a locked state

Abstract: A method and system for managing global queues is provided. In one example, a method for implementing a global queue is provided. The queue has a head pointer, a tail pointer, and zero or more elements. The method comprises one or more functions for managing the queue, such as an “add to end” function, an “add to front” function, an “empty queue” function, a “remove from front” function, a “remove specific” function and/or a “lock queue” function. In some examples, the method enables an element to be added to the queue even when the queue is in a locked state.

Method,apparatus, and computer program product for implementing packet ordering

Abstract: A method, apparatus, and computer program product are provided for implementing packet ordering in a network processor. Packets are received and placed on a receive queue and a queue entry is provided for each received packet. The queue entry includes for each autoroute packet, an autoroute indication and a selected transmit queue. An associated ordering queue is provided with the receive queue. A software-handled packet is dequeued from the receive queue and the dequeued software-handled packet is placed on the ordering queue. Each autoroute packet reaching a head of the receive queue is automatically moved to the selected ordering queue.