Showing papers on "Sequential logic published in 1971"

A Heuristic Algorithm for the Testing of Asynchronous Circuits

Abstract: This paper describes an algorithm for the computation of tests to detect failures in asynchronous sequential logic circuits. It is based upon an extension of the D-algorithm [1]. Discussion of experience with a program of the procedure is given.

A Random and an Algorithmic Technique for Fault Detection Test Generation for Sequential Circuits

Abstract: Two procedures are presented for generating fault detection test sequences for large sequential circuits. In the adaptive random procedure one can achieve a tradeoff between test generation time, length, and percent of circuit tested. An algorithmic path-sensitizing procedure is also presented. Both procedures employ a three-valued logic system. Some experimental results are given.

Algorithms for Detection of Faults in Logic Circuits

Abstract: Programmed algorithms for test generation and test evaluation are described. The D-notation is introduced and a test generator (DALG) for combinational logic is presented. The sequential case is then examined. "Real life" constraints related to LSI testing are discussed. Two heuristic test generators satisfying these constraints are introduced. The iterative test generator (ITG) generates tests by transforming the given sequential circuit into an iterative combinational circuit. The macroblock test generator (MTG) uses the same approach but makes use of complex primitives (latches, triggers, etc.) to represent the circuit to be tested. Both the ITG and the MTG are not always guaranteed to generate good tests for each examined failure, and are used in connection with a test evaluator (simulator). Basic features of this evaluator are discussed.

Limited vocabulary speech recognition circuit for machine and telephone control

Abstract: Machine or telephone control by voiced commands is attained by translating the electrical signal derived from an acoustic signal or spoken word into a plurality of binary parameter waveforms each indicating sequentially the instantaneous condition or measurement of the corresponding parameter in terms of its being on either one side or the other of a preselected threshold or norm. A command output signal is generated only when the waveforms are found to have a particular sequence of binary parameter combinations that is acceptable to a sequential logic recognition circuit.

Sequential Machine Identification

Abstract: A special aspect of sequential machine identification is treated in this paper. Given an input signal sequence to an unknown sequential machine and the resulting output signal sequence of the machine, it is necessary to find a state table or any other description of the machine and all other machines which response to the given input sequence with the given output sequence. The main objective of the research was to develop a fast and efficient state merging method which profits from the special characteristics of the problem at hand.

State Assignments for Asynchronous Sequential Machines

Abstract: In this paper, a heuristic state assignment algorithm for asynchronous sequential machines is presented. Machines realized by this assignment scheme will result in circuits having a small amount of gate inputs and operating in single transition time. It is also shown that for a flow table having m 1 input columns, m input variables, and d stable states, the number of gate inputs required for a single transition time realization is bounded by d(m 1 +m+1).

Large-scale integrated circuit testing structure

Abstract: A plurality of sequential logic circuits are connected to a shift register, both located on the same semiconductor chip. Input test data supplied at a chip input pad is routed via parallel paths interconnecting the sequential logic circuits to the shift register for performing combinatorial logic tests. The test responses are accessible to a chip output pad via the shift register. The shift register functions as virtual input/output pads so as to permit combinatorial logic testing on high density sequential logic circuits without increasing the actual input/output pad requirements of the semiconductor chip.

Boolean Difference for Fault Detection in Asynchronous Sequential Machines

Abstract: The progress in integrated circuits or large-scale integration (LSI) has increased the difficulty of testing and diagnosis. This paper extends the early results of using Boolean difference to generate test patterns for sequential circuits. The theory described in this paper is based on an extended Boolean difference definition, which gives a solution to the problem of automatic generation of test patterns for asynchronous sequential circuits. A complete program written in Fortran has been tested on various examples. Results are very close to the theoretical expectation.

Realization Methods for Asynchronous Sequential Circuits

Abstract: This paper gives a unified approach for describing various systematic ways of using built-in delays in normal fundamental mode circuits. The transition of the circuit from one total stable state to another is characterized by the constraints imposed upon the next-state functions, and the realization method is characterized by the conditions under which these constraints can be satisfied simultaneously.

Multiple phase clock generator circuit with control circuit

Abstract: A clock signal generating circuit including an oscillator circuit for supplying complementary square wave signals. A control circuit connected to the oscillator circuit for receiving the square wave signals and for, providing phase inversion and ordering of the signals in order to prevent phase overlap between the complementary signals. The output signals from the control circuit provide gating signals for a shift register. Output signals from the shift register are provided as input signals to output logic gates for generating multiple phase output signals. The output logic gates receive feedback signals from certain of the output logic gates for synchronizing the phase relationship between the multiple phase clock signals produced by the output logic gates.

Electronic traffic signal control system

Abstract: An electronic traffic signal control system. Logic circuitry is included for providing a sequence of timed changing logic states which define operating periods for a plurality of signal lights. Control means is responsive to the changing logic states for selectively energizing predetermined ones of the signal lights during each of respective operating periods defined by the logic states. Timing circuitry generates timing pulses for causing successive changing of the logic states. Provision is made for manually varying the timing of generation of the timing pulses for preselecting the lengths of the respective operating period defined by each of the logic states.

Threshold logic digital filter

Abstract: A threshold logic digital filter converts an input sequence of sets of bits representing amplitudes of a continuous signal at predetermined sample times into another sequence of sets of bits representing the input sequence of sets transformed by a predetermined difference equation. Storage-processor elements are used for implementing threshold logic adder, multiplier, two''scompartment, and overflow detector circuits in the digital filter.

High speed/logic circuit

Abstract: A high speed logic circuit comprising a plurality of unit gate circuits, wherein each transistor in the unit gate operates between cut-off and within an active region bounded by the saturation region of the gate transistor in response to first and second logic level input signals. Each transistor gate is connected in the common emitter configuration; the collector resistance is greater than the sum of the emitter series resistance and the incremental junction emitter resistance of the gate transistor with an input signal exceeding the base-toemitter voltage of the gate transistor. The voltage source has a voltage which is insufficient for the gate transistor to which a first logic level signal is applied to be switched to an active state from a non-conducting state. Further, the collector current of the gate transistor is limited by the emitter series resistor when the second logic level signal is applied so that the collector junction thereof does not inject minority carriers. The potential difference between the voltage source terminals is defined by the formulas

Logic circuit delay system comprising monostable means for providing different time delays for positive and negative transitions

Abstract: A logic circuit having a single monostable circuit operating a flip-flop circuit and means controlled by the latter to switch resistance values in an RC circuit of the monostable for establishing different time delays for positive and negative logic transitions.

A State Assignment Procedure for Asynchronous Sequential Circuits

Abstract: This paper presents a new procedure for constructing nonuniversal shared-row internal state assignments for asynchronous sequential circuits. The method consists basically of establishing an initial code with the minimum number of variables required to distinguish the states. satisfactory assignment is obtained. State variables added in the expansion of an assignment are merely the EXCLUSIVE OR of state variables in the original assignment. This simple construction procedure terminates with a maximum of m+[m/2] state variables for a 2m-row flow table.

Self-checking combinational logic counter circuit

Abstract: A self-checking combinational logic counter providing three predicted parity change bits. One of the bits is derived by logic independent of the counting logic, the other two bits being derived by logic dependent upon the operation of the counting logic. The three bits are compared to detect a match indicating an accurate prediction of a parity change or retention of original parity.

The Avoidance and Elimination of Function Hazards in Asynchronous Sequential Circuits

Abstract: Armstrong et al.[1] have shown how critical races and function hazards can be suppressed in asynchronous sequential circuits by using gate delays to advantage rather than introducing explicit delay elements, if certain delay assumptions are satisfied. This paper shows that the same techniques may be used to design circuits which will respond reliably to simultaneous changes of several input variables.

Three state output logic circuit with bistable inputs

Abstract: A three output state logic circuit includes the last cell of a shift register, which is a flip-flop, coupled to an RS type flip-flop which drives a push-pull output circuit. The output circuit is placed in a high impedance or floating logic state by grounding the output terminals of the RS flip-flop. The effect of this grounding is, however, isolated from the last cell of the shift register so that it maintains its stored binary information.

Logic circuitry for monitoring the cyclic operations of a pair of devices

Abstract: Logic circuitry is utilized to monitor the continued cyclic operation of a pair of devices, e.g., strand feeding devices. As the devices function a pair of trains of pulses are generated and the logic circuit detects and generates a malfunction signal upon the generation of two pulses within one train without the intervening generation of a pulse in the other train. The logic circuit accepts concurrent generation of pulses, and the subsequent reversal of the lead pulse in the trains without the generation of malfunction signals. Facilities are also provided to allow the devices to commence operation independent of control by the logic circuits.

Pulse Input Asynchronous Sequential Circuits

Abstract: Traditionally, synchronous sequential circuits are considered controlled by input pulses, and asynchronous sequential circuits by input levels. The aim of this note is to study the general properties of a class of asynchronous circuits with some inputs that can be thought of as driven by "pulses." The synthesis process and the internal structure of these circuits, called pulse input asynchronous sequential circuits (PA circuits), are investigated, and they are compared with pulse input synchronous circuits and with level input asynchronous circuits. Procedures are described to transform any flow table describing a synchronous circuit into a flow table describing an equivalent PA circuit, and to realize any normal mode asynchronous circuit by a PA circuit. Specific techniques for PA circuit state reduction and PA circuit state assignment are described in other papers.

The Realization of Polylinear Sequential Circuits Using Flip-Flop Memory

Abstract: In this paper there are developed simple processes for deriving, for finite synchronous sequential machines, polylinear sequential circuit realizations using trigger, set–reset, or J–K flip-flops as the memory elements. It is shown that each such realization is directly obtainable from a graph analogous to the reverse state diagram of the given machine; the latter graph was shown in a former paper by this author to correspond to a polylinear sequential circuit realization using delays for memory. The processes consist of the straightforward steps in the construction of the reverse state diagram analogs. Almost polylinear sequential circuits are defined, and it is shown how certain proper subgraphs of the aforementioned graphs can be used to derive these circuits.

A simple charge regenerator for use with charge-coupled and bucket-brigade shift registers and the design of functional logic arrays

Abstract: A charge-inversion regenerator for use with charge-coupled and bucket-brigade shift registers has been developed. The configuration of this regenerator and its use in functional self-regenerating memory, logic arrays, shift address and control systems will be described.

Designing Sets of Fault-Detection Tests ror Combinational Logic Circuits

Abstract: This paper is concerned with the problem of determining, by means of terminal experiments, whether a given combinational switching circuit operates correctly or is impaired by some malfunction. We shall be primarily concerned with permanent faults due to component failures. It is assumed that other methods will be employed to protect the circuit against the effects of transient faults. A procedure is presented for the detection of failures in combinational switching circuits. The procedure provides minimal sets of tests for two-level circuits and nearly minimal sets of tests for most multilevel circuits.

A Universal STT State Assignment Method for Pulse Input Asynchronous Sequential Circuits

Abstract: Methods to realize race-free asynchronous sequential circuits by using appropriate single transition time (STT) state assignments have been described in the literature. This paper deals with that restricted class of asynchronous circuits (called pulse-input asynchronous circuits) for which in every input sequence each input state l i is always followed by a special input state l o ≠l i . A method is presented to realize any pulse-input asynchronous sequential circuit with p internal states by a universal race-free STT state assignment in 2E o variables, where E o =[log 2 n] and n≤p is the number of the elements in a defined subset of internal states.

Threshold logic circuits

Abstract: The invention is a threshold logic circuit including a pair of busses and a plurality of storage-processor elements connected to the busses. Each element is arranged to decide which one of a pair of double-rail input signals has a higher potential and to store the result of that decision. Information read out of storage directs a unit of current alternatively to one or the other of the two busses. A threshold logic adder circuit and a threshold logic two''scomplement circuit are included.

Race analysis of digital systems without logic simulation

Abstract: Critical timing races (hazards) are a potential problem in digital systems consisting of a large number of interchangeable modules and replaceable integrated circuits. These hazards can be minimized by careful design procedures and reviews but will still exist due to system complexities. Systems have been proposed for simulating digital networks based on a time-sequenced logical tracing, but these systems require much host computer time and input stimuli to thoroughly exercise the system. The basis of the proposed race analysis system is that all critical races result in an improper flip-flop state. Each flip-flop input is traced, from logic element out-put to input, accumulating delays. Two basic algorithms are required and described to locate the racing of parallel paths on flip-flop inputs. This system requires minimal user inputs and can perform either a statistical or worst case race analysis.

Digital sequential circuit

Abstract: A multi-state digital sequential circuit of unified logic elements provided for sequential testing of single-bit signals and passing into selected states or producing single-bit output signals according to arbitrarily present algorithm. The circuit consists of a plurality of unified elements comprising interconnected flip-flops, inverters, AND-circuits, and OR circuits.

Alternating current static control system

Abstract: An alternating current solid state control system utilizing alternating current AND and OR alternating current solid state control logic elements The alternating current logic elements perform their logic functions by comparing the voltage drop across a resistor to a predetermined reference voltage, the voltage drop being caused by the logical input state of the logic element Each element''s output can be used as a feedback to its own inputs or can be connected to the inputs of electrically similar circuits By the use of multiple logical inputs, various feedback connections, and various combinations of the alternating current logic elements complex logic functions can be generated to control mechanical apparatus