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Showing papers on "Silicon oxide published in 1980"


Patent
27 Nov 1980
TL;DR: A voltage-dependent resistor for a lightening arrester and a surge absorber comprises a sintered zinc oxide body of a composition which comprises, as additives, 0.1 to 3.5 mole percent of chromium oxide (Cr2O3), at least one member selected from the group consisting of 0.00005 to 0.
Abstract: A voltage-dependent resistor for a lightening arrester and a surge absorber comprises a sintered zinc oxide body of a composition which comprises, as additives, 0.1 to 3.0 mole percent of bismuth oxide (Bi2O3), 0.1 to 3 mole percent of cobalt oxide (Co2O3), 0.1 to 3 mole percent of maganese oxide (Mn02), 0.1 to 3.0 mole percent of antimony oxide (Sb2O3), 0.05 to 1.5 mole percent of chromium oxide (Cr2O3), at least one member selected from the group consisting of 0.1 to 10 mole percent of silicon oxide (Si02) and 0.1 to 3 mole percent of nickel oxide (NiO), at least one member selected from the group consisting of 0.0005 to 0.025 mole percent of aluminum oxide (Al2O3) and 0.005 to 0.025 mole percent of gallium oxide (Ga2O3), and 0.005 to 0.3 mole percent of boron oxide (B2O3), and if necessary, 0.00005 to 0.3 mole percent of silver oxide (Ag2O), with electrodes applied to opposite surfaces of the sintered body. The resistor has a non-ohmic property (voltage-dependent I property) due to the bulk itself. Therefore, its C-value can be changed without impairing its n-value by changing the distance between the electrodes at opposite surfaces.

53 citations


Journal ArticleDOI
TL;DR: In this article, it was shown that reactive neutral fragments, generated by multiple infrared photon dissociation of various molecules with a laser, are capable of etching silicon oxide or nitride surfaces.
Abstract: We have found that reactive neutral fragments, generated by multiple infrared photon dissociation of various molecules with a laser, are capable of etching silicon oxide or nitride surfaces. The laser‐generated radical etching process has a potential for major commercial impact, by eliminating ion‐bombardment damage in the resulting semiconductor device and by permitting more efficient and selective etching to be performed. In addition, this provides an investigative tool for learning the precise identity of the active species, the extent of their interaction with the substrate surface, and the rates of the key steps in the reactions resulting in net removal of silicon.

52 citations


Patent
01 Apr 1980
TL;DR: In this paper, an n-channel 1st impurity region 121 and the 2nd bit line 122 are provided on a p type silicon substrate and a selection electrode layer 14 used as a word line is formed between the regions 121 and 122 via a gate oxide film 13.
Abstract: PURPOSE:To attain high density and low power consumption of a nonvolatile semiconductor memory by forming a memory of an impurity region, an insulating layer, and an electrode layer or the like, constituted in a prescribed way on a substrate, and reading dynamically the stored electric charge. CONSTITUTION:An n-channel 1st impurity region 121 and the 2nd impurity region 122 used as a bit line are provided on a p type silicon substrate 11 and a selection electrode layer 14 used as a word line is formed between the regions 121 and 122 via a gate oxide film 13. On the other hand, a control gate electrode layer 19 or the like via a gate oxide film 15, field oxide film 16, floating gate electrode layer 17 and a poly silicon oxide film 18 in constant with the region 121 is laminated to form the nonvolatile semiconductor memory. Through the constitution above, the presence of an electric charge of the layer 17 is read by the dynamic detection of a charge amount stored in a capacitor made of the layer 17 and the substrate 11, the source region of a storing transistor, its wiring and a decoder or the like are not required and the high density and low power consumption of the nonvolatile semiconductor memory are attained.

47 citations


Patent
Robert E. Holmes1
09 Jan 1980
TL;DR: In this paper, thin-film microcircuit structures passivated with silicon nitride are provided in which included electrical components containing nickel, chromium or other nitride-forming metals are encapsulated in an oxide material, preferably silicon oxide.
Abstract: Thin-film microcircuit structures passivated with silicon nitride are provided in which included electrical components containing nickel, chromium or other nitride-forming metals are encapsulated in an oxide material, preferably silicon oxide. The metal-containing components are thus prevented from reacting with the silicon nitride passivation coating during through-passivation laser trimming of the components.

30 citations


Patent
28 Apr 1980
TL;DR: In this paper, a transparent monolithic member or coating on a substrate consisting of aluminum and silicon in an atom ratio of about 2:1 and in reacted oxide form is presented.
Abstract: High-temperature-resistant transparent monolithic member or coating on a substrate consisting of aluminum and silicon in an atom ratio of about 2:1 and in reacted oxide form. The member or coating is formed by reacting precursor alkoxides of aluminum and silicon in the presence of water or reacting precursors derived from these alkoxides, gelling the reacted precursors, and drying the gel in the form of a monolithic member or coating. The dried member is then heated to evolve all residual hydrogen and carbon and residual water and to eliminate porosity to form the monolithic member or coating.

28 citations


Patent
30 May 1980
TL;DR: In this paper, a patterned thin silicon oxide layer is formed by thermally-oxidizing the epitaxial layer having a buried layer and, at the same time, the isolation region is formed in the epitxial layer by heating for thermal oxidation.
Abstract: In a case where a semiconductor device is produced comprising at least one semiconductor element, an isolation region surrounding the semiconductor element and a thick silicon oxide layer lying on and around the semiconductor element, the thick oxide layer is formed by thermally-oxidizing the epitaxial layer having a buried layer and, at the same time, the isolation region is formed in the epitaxial layer by heating for thermal oxidation Prior to a step of introducing impurities into the epitaxial layer, a patterned thin silicon oxide layer is formed This thin silicon oxide layer is varied into the thick oxide layer by the thermal-oxidation treatment

23 citations


Patent
28 Feb 1980
TL;DR: In this article, a method of applying thin metal sensitizing deposits to the exposed silicon areas of a silicon substrate having areas of exposed silicon and silicon oxide was proposed, including the steps of immersing the silicon substrate in a basic, aqueous solution containing a metal salt of the metal to be deposited, particularly a nickel, cobalt, or platinum salt, and thereafter reducing the metal ion of the salt to the elemental metal by use of the uncovered silicon as the reducing agent.
Abstract: A method of applying thin metal sensitizing deposits to the exposed silicon areas of a silicon substrate having areas of exposed silicon and silicon oxide, including the steps of immersing the silicon substrate in a basic, aqueous solution containing a metal salt of the metal to be deposited, particularly a nickel, cobalt, or platinum salt, and thereafter reducing the metal ion of the salt to the elemental metal by use of the exposed silicon as the reducing agent.

22 citations


Journal ArticleDOI
TL;DR: In this article, the authors examined the relationship between chemical reactions on interstellar grains and their optical properties, and concluded that pure Fe grains are unlikely to exist in the diffuse ISM (interstellar medium) because of low-temperature oxidation to Fe oxides by O atoms.
Abstract: Possible relationships between chemical reactions on interstellar grains and their optical properties are examined. A variety of reactions that will lead to chemical reduction or oxidation are discussed. To illustrate possible processes, the equilibrium in the Fe oxide series (Fe, FeO, Fe/sub 3/O/sub 4/, Fe/sub 2/O/sub 3/) as a function of ambient conditions has been investigated. One immediate conclusion from this study is that pure Fe grains are unlikely to exist in the diffuse ISM (interstellar medium) because of low-temperature oxidation to Fe oxides by O atoms. It is shown that several optical effects customarily ascribed to size changes in dust can be interpreted in terms of chemically induced modifications in the optical properties of dust. As an example, the optical properties of the silicon oxide series SiO/sub x/, where 1< or =x< or =2, is used to investigate a possible relationship between refractive index variations and variations in the lambda/sub max/, the wavelength of maximum linear polarization. Reduction of silicate or oxide grains in H II regions may be related to OH and H/sub 2/O maser sources observed in these regions.

22 citations


Patent
29 Apr 1980
TL;DR: A method of manufacturing a semiconductor device comprises the steps of forming an interconnection electrode made of a refractory metal or a silicide of the metal on an insulating film formed on an semiconductor substrate with necessary elements already formed, forming a silicon oxide film on the silicon nitride film, thereby preventing the elements from being deteriorated as discussed by the authors.
Abstract: A method of manufacturing a semiconductor device comprises the steps of forming an interconnection electrode made of a refractory metal or a silicide of the metal on an insulating film formed on a semiconductor substrate with necessary elements already formed, forming a silicon nitride film on the interconnection electrode, and forming a silicon oxide film on the silicon nitride film, thereby preventing the elements from being deteriorated.

21 citations


Patent
12 Aug 1980
TL;DR: In this paper, the authors proposed a novel method of manufacture which reduces the problem of disconnection of electrode interconnections, which promotes the fineness of a pattern based on self-alignment and reduces the capacitance between source and drain electrodes thereby to achieve a high speed operation.
Abstract: In the manufacture of a field-effect transistor, a silicon nitride film (underlaid with a thin silicon oxide film) is selectively formed on those parts of a semiconductor substrate of a first conductivity type at which a gate region and source and drain electrodes are to be formed, the formation of the source and drain regions and subsequently the formation of a selective thermal oxidation film on the source and drain regions are carried out by employing the silicon nitride film as a mask, and thereafter, the silicon nitride film is removed and the contacts are selectively formed at the exposed parts. Further, this invention extends to the manufacture of a C-MOS integrated circuit device which exploits the SOP (Selective oxidation process) technique employing an oxidation-proof film. According to this invention, there are provided a novel method of manufacture which reduces the problem of disconnection of electrode interconnections, which promotes the fineness of a pattern based on self-alignment and which reduces the capacitance between source and drain electrodes thereby to achieve a high-speed operation.

21 citations


Patent
Else Kooi1
25 Sep 1980
TL;DR: An insulated gate field effect transistor and a method of making same, in which the channel was provided in a mesa region of a silicon body, and the channel is surrounded by thicker silicon oxide over the adjacent source and drain regions.
Abstract: An insulated gate field-effect transistor and a method of making same, in which the channel is provided in a mesa region of a silicon body, and the channel is surrounded by thicker silicon oxide over the adjacent source and drain regions. A thinner insulating layer is over the channel, and a gate electrode on the latter. The manufacturing method involves masking the channel region while growing silicon oxide around it causing the oxide to penetrate into the silicon areas surrounding the channel to provide the channel in a mesa surrounded by the oxide.

Patent
10 Oct 1980
TL;DR: In this article, the ratio of the thermal energy supplied to the furnace to the amount of silicon oxide supplied by the furnace is made adjustable in such a manner that a value for the ratio can be set within an interval, which interval in its lower end is limited by the lowest value permitting constant reduction of the silicon monoxide and silicon directly with a certain part of the reducing agent which is supplied at the top of the furnace, and in its upper end is restricted by the highest value permitting the silicon oxide raw material to be converted to silicon carbide.
Abstract: A process for the production of silicon or ferrosilicon by reduction of silicon oxide, optionally in the presence of iron or iron oxide, using a carbonaceous reducing agent, in a reduction furnace. The yield is improved without harmful temperature rises if the ratio of the amount of thermal energy supplied to the furnace to the amount of silicon oxide supplied to the furnace is made adjustable in such a manner that a value for the ratio can be set within an interval, which interval in its lower end is limited by the lowest value permitting constant reduction of the silicon monoxide and silicon directly with a certain part of the reducing agent which is supplied at the top of the furnace, because the amount of produced silicon monoxide is insufficient for complete conversion of all the carbonaceous reducing agent to silicon carbide at the top of the furnace, and in its upper end is limited by the highest value permitting constant reduction of the silicon oxide raw material to silicon monoxide and silicon di- retcly with silicon carbide, because the amount of produced silicon monoxide is sufficient for conversion of the carbonaceous reducing agent to silicon carbide at the top of the furnace, and that a sufficient content of reducing agent is maintained in the lower, hotter, parts of the furnace so that reduction to some extent can take place directly with the reducing agent.

Patent
08 Jul 1980
TL;DR: In this paper, a double self-alignment of the grid electrodes was achieved by placing a silicon nitride layer between a first silicon oxide layer developed on a silicon wafer and a second silicon dioxide layer developed from polycrystalline silicon grid electrodes.
Abstract: The process of the invention allows, by placing a silicon nitride layer between a first silicon oxide layer developed on a silicon wafer and a second silicon oxide layer developed from polycrystalline silicon grid electrodes, a double self-alignment of the grid electrodes to be obtained which are used as a mask with respect to the channel-forming zones of the transistor and of these same grid electrodes used as a mask with respect to the connections for the source regions of this same transistor, the source regions being obtained by diffusion in the silicon wafer of the dopant of a doped polycrystalline silicon layer forming the connections of the source regions.

Patent
14 Feb 1980
TL;DR: In this article, a method for producing powder of.alpha-silicon nitride which comprises the steps of: adding 0.3 to 2 parts by weight of powder of carbon and 0.005 to 1 part of at least one silicon compound selected from the group consisting of Si3N4, SiC and silicon oxide nitride series compounds to one part by weight (as converted to SiO 2) of a liquid silane derivative which produces a precipitate and HCl by hydrolysis and further causes SiO2 to be grown by the baking of said precipitate,
Abstract: of the Disclosure A method for producing powder of .alpha.-silicon nitride which comprises the steps of: adding 0.3 to 2 parts by weight of powder of carbon and 0.005 to 1 part by weight of at least one silicon compound selected from the group consisting of Si3N4, SiC and silicon oxide nitride series compounds to one part by weight (as converted to SiO2) of a liquid silane derivative which produces a precipitate and HCl by hydrolysis and further causes SiO2 to be grown by the baking of said precipitate, or the precipitate produced by hydrolysis of the liquid silane derivatives; hydrolyzing the resultant mixture, if necessary; washing the mixture to separate a solid component, if necessary; and baking the solid component for reduction and nitro-genization at a temperature of 1300° to 1500°C in an atmosphere mainly consisting of a nitrogen gas or a gas of a nitrogen compound.

Patent
Hisao Yakushiji1
07 Jan 1980
TL;DR: In this article, a method for manufacturing semiconductor devices having a multi-layer wiring interconnection structure was proposed, in which a first interconnection wiring metal layer is formed on a semiconductor substrate followed by the formation of layers of silicon nitride on portions wherein patterns are to be placed and forming a layer of silicon oxide over the layer.
Abstract: A method for manufacturing semiconductor devices having a multi-layer wiring interconnection structure wherein a first interconnection wiring metal layer is formed on a semiconductor substrate followed by the formation of layers of silicon nitride on portions wherein patterns are to be placed and forming a layer of silicon oxide over the layer of silicon nitride. Selective portions of the silicon oxide layer are removed by lightly etching the layer to form recesses around the wiring portions of the metal layer. The silicon nitride layer is then removed and an insulating layer is formed on the surface from which the silicon nitride layer was removed. Through-holes are formed in predetermined portions of the insulating layer through which contact is made to a second wiring metal layer disposed over the insulating layer.

Patent
05 Dec 1980
TL;DR: In this paper, a surface acoustic wave device is presented which comprises a multi-layered substrate consisting of at least a piezoelectric zinc oxide layer, an intermediate silicon oxide layer and an α-Al2 O3 base made of a single crystal.
Abstract: This invention provides a surface acoustic wave device which comprises a multi-layered substrate. The multi-layered substrate comprises at least a piezoelectric zinc oxide layer, an intermediate silicon oxide layer and an α-Al2 O3 base made of a single crystal havine an (0112) crystallographic plane or an equivalent crystallographic plane. This surface acoustic wave device is operable at ultra-high frequency.

Patent
08 Oct 1980
TL;DR: In this paper, a voltage nonlinear resistor comprising a sintered body composed mainly of zinc oxide is described, including confronting main faces and a face side face connecting the main faces to each other, with the side face coated with a coating glass layer containing barium oxide.
Abstract: Disclosed is a voltage non-linear resistor comprising a sintered body composed mainly of zinc oxide, said sintered body including confronting main faces and a face side face connecting the main faces to each other, which has the side face coated with a coating glass layer containing barium oxide. The coating glass layer comprises 40 to 85% by weight of lead oxide, 3 to 25% by weight of boron oxide. 1.5 to 25% by weight of silicon oxide and 0.2 to 15% by weight of barium oxide. The barium oxide acts as a catalyst and exerts a function of completely burning an organic binder at a temperature lower than about 400° C. where the reaction between the organic binder and zinc oxide is not substantially advanced.

Patent
10 Dec 1980
TL;DR: In this paper, an alcohol solution containing 5W30wt% organic silicon compound (e.g. ethyl silicate) is added with a zirconium compound[e] in an amount of 1W30mol% (as ZrO 2 ), and the pH of the mixture is adjusted to 2W6 with an acid such as hydrochloric acid, acetic acid, etc.
Abstract: PURPOSE: To prepare the titled substrate coated with silicon oxide having high stability against saline water and high-temperature steam, by forming a silicon oxide coating film containing ZrO 2 on the surface of a substrate. CONSTITUTION: An alcohol solution containing 5W30wt% organic silicon compound (e.g. ethyl silicate) is added with a zirconium compound[e.g. ZrCl 2 , Zr(NO 3 ) 4 , etc.]in an amount of 1W30mol% (as ZrO 2 ), and the pH of the mixture is adjusted to 2W6 with an acid such as hydrochloric acid, acetic acid, etc. to obtain a film-forming solution. The solution is applied to the surface of a substrate made of glass, ceramic, plastic, etc., dried by heating, and baked in an oxidative atmosphere or in air at 300W650°C to obtain a silicon oxide coating film having a thickness of 500W2,000Å. The silicon oxide coating film thus obtained is resistant to the formation of spot defects and fine cracks even by the outdoor exposure. COPYRIGHT: (C)1982,JPO&Japio

Patent
02 Jun 1980
TL;DR: In this article, a method for manufacturing a semiconductor device having a high breakdown voltage and a high reliability, consisting of forming an undoped poly-silicon layer (16) on the impurity-doped polysilicon (15) having a diffusion window, and thermally oxidizing the substrate with the insulating layer (13), impurity doped poly(silicon) layer (15), silicon oxide layer (18), and mask layer (19) in a desired pattern, is presented.
Abstract: A method for manufacturing a semiconductor device having a high breakdown voltage and a high reliability, comprises (a) forming on a semiconductor substrate (12) an insulating layer (13) having a diffusion window (14); (b) forming an impurity-doped poly-silicon layer (15) on the insulating layer (13) and on that portion of the semiconductor substrate (2) which is exposed through the diffusion window (14); (c) forming an undoped poly-silicon layer (16) on the impurity-doped poly-silicon layer (15); (d) thermally oxidizing the substrate (2) with the insulating layer (13), impurity-doped poly-silicon layer (15) and undoped poly-silicon layer (16), thus diffusing the impurity from the impurity-doped poly-silicon layer (15) into the semiconductor substrate (12) through the diffusion window (14) and converting the undoped poly-silicon layer (16) to a silicon oxide layer (18); (e) forming on the silicon oxide layer (18) an oxidation-resisting mask layer (19) in a desired pattern; and (f) thermally oxidizing the substrate (12) with the insulating layer (13), impurity-doped poly-silicon layer (15), silicon oxide layer (18) and mask layer (19), thus converting those portions of the impurity-doped poly-silicon layer (15) which lie beneath those portions of the silicon oxide (18) layer which are exposed through the mask layer (19) to impurity-doped silicon oxide layers, whereby the remaining portions of the impurity-doped poly-silicon layer provide an interconnection electrode layer (21) having a desired pattern.

Journal ArticleDOI
TL;DR: In this article, measurements of I-V, G-V and C-V characteristics were taken on MIS tunnel junctions where M is a metal, I is silicon oxide, and S is hydrogenated amorphous silicon, a-Si:H.
Abstract: Measurements of I-V, G-V, and C-V characteristics were taken on MIS tunnel junctions where M is a metal, I is silicon oxide, and S is hydrogenated amorphous silicon, a-Si:H. The results indicate a peak in the density of states which lies 0.45 eV below the conduction-band edge. The states distribution concluded from the present study is in good agreement with the conclusions based on field-effect measurements.

Patent
Paul J. Van Assche1
24 Nov 1980
TL;DR: In practice no sealing glasses are known with which glass or ceramic material having a coefficient of thermal expansion α 30 °-300° C. can be sealed together as discussed by the authors, in the range between 31 to 36×10 -7 per °C.
Abstract: In practice no sealing glasses are known with which glass or ceramic material having a coefficient of thermal expansion α 30 °-300° C. in the range between 31 to 36×10 -7 per °C. can be sealed together. The invention provides bodies which are composed of at least two parts, these parts having been made from a material having a coefficient of expansion as mentioned above, the parts having been sealed together by means of a sealing glass containing 8-10 weight % vanadium pentoxide, 1.5-3.0 weight % copper (II) oxide, 1-3 weight % lead (II) oxide, 0-1 weight % silicon oxide, 0-5 weight % aluminium oxide, 26-28 weight % boron oxide and 58-61 weight % zinc oxide. The weight ratio of boron oxide to zinc oxide is in the range from 0.45 to 0.47. The body is composed of parts (1 and 3), which have been sealed together by means of the sealing glass (2).

Patent
08 Sep 1980
TL;DR: A voltage nonlinear resistor comprises a sintered body of a ceramic composition comprising zinc oxide at a ratio of 99.88 to 84.88 mol % as ZnO; a praseodymium oxide component at the ratio of 0.0001 to 0.05 mol %; and a cobalt oxide component with a ratio between 0.1 to 15mol % as CoO and a specific additional component selected from chromium oxide, boron oxide, silicon oxide, titanium oxide, tin oxide, zirconium oxide and germanium oxide as mentioned in this paper
Abstract: A voltage non-linear resistor comprises a sintered body of a ceramic composition comprising zinc oxide at a ratio of 99.88 to 84.88 mol % as ZnO; a praseodymium oxide component at a ratio of 0.01 to 0.035 mol % as Pr 2 O 3 and a lanthanum oxide component at a ratio of 0.01 to 0.035 mol % as La 2 O 3 and a cobalt oxide component at a ratio of 0.1 to 15 mol % as CoO and a specific additional component selected from chromium oxide, boron oxide, silicon oxide, titanium oxide, tin oxide, zirconium oxide, niobium oxide, tantalum oxide, tungsten oxide and germanium oxide at a ratio of 0.0001 to 0.05 mol %.

Patent
Hirobe Kadou1
26 Jun 1980
TL;DR: In this article, the depth and width of the ridge and the geometry of their side walls are selected so as to provide a continuity of silicon oxide films, formed during heat treatment of the silicon substrate.
Abstract: The formation of a thick silicon oxide layer is intended primarily for integrated circuit of metal-oxide-semiconductor (MOS) and bipolar type. The layer is to be produced in a given region of a suitable semiconductor substrate, whose production is the first step of the process. Then the material of the substrate is selectively removed and parallel grooves are formed in the given region. Ridges are similarly formed between adjacent grooves. The depth and width of the grooves and the geometry of their side walls are selected so as to provide a continuity of silicon oxide films, formed during heat treatment of the silicon substrate. The width of a ridge between two adjacent grooves also permits the formation of a silicon oxide film during heat treatment, which is carried out in an oxidising atmosphere which converts the ridges into silicon oxide and fills the grooves with this oxide. Pref. the width of the ridges is smaller than that of the grooves.

Journal ArticleDOI
TL;DR: In this article, the cathodic current through a thermally grown silicon oxide layer on silicon in aqueous solution is examined, and it is found that the current flows through localized areas of the oxide, through flaws.

Patent
19 Jun 1980
TL;DR: In this article, a low-expansion ceramic material is described, which consists of from 1.2 to 20% by weight of Magnesia, from 6.5 to 68% of alumina, from 19 to 80% of titanium dioxide, and from 1 to 20 percent of silica, with a melting point of not less than 1500°C.
Abstract: The present invention relates to low-expansion ceramic material, the chemical composition of which consists of from 1.2 to 20% by weight of magnesia, from 6.5 to 68% by weight of alumina, from 19 to 80% by weight of titanium (calculated as titanium dioxide), from 1 to 20% by weight of silica, and from 0.5 to 20% by weight of iron (calculated as ferric oxide); the major component of the crystalline phase of the material being a magnesium oxide/aluminum oxide/titanium dioxide/silicon oxide/iron oxide solid solution; and the material having a coefficient of thermal expansion of not more than 20x1o- 7 (1/°C) in the temperature range 25°C to 800°C, a four-point flexural strength of not less than 50 kg/cm 2 at room temperature, and a melting point of not less than 1500°C. The material is prepared by forming a batch of magnesia, alumina, titanium oxide, silica and iron oxide (as such or in the form of precursors therefor capable of being converted thereto on firing); plasticizing the batch if necessary and shaping the batch; thus shaped; and firing the shaped body at 1300°C to 1700°C. The ceramic material is suitably in the form of a honeycomb structure.

Patent
29 Jan 1980
TL;DR: In this paper, the side surface of a multi-crystal silicon is covered with an insulation film so that occurrence of emit ter-base shortcirciut due to contact between the multi-Crystal silicon and a base electrode can be eliminated.
Abstract: PURPOSE:To increase production recovery and improve quality by covering side surface of a multi-crystal silicon with an insulation film so that occurrence of emit ter-base shortcirciut due to contact between the multi-crystal silicon and a base electrode can be eliminated. CONSTITUTION:A silicon oxide film 22 on an N type semiconductor base plate 21 is provided with a hole, and P type impurity is dispersed to form a base region 23, and then, a multi-crystal silicon 24 is allowed to develop gaseous growth. A silicon nitride film 25 is selectively formed, and etching of the multi crystal silicon 24 is processed. After an entire surface of the silicon oxide film 26 has been covered, impurity is dispersed to form an emitter region 27. Ion is injected onto an entire surface. The silicon oxide film 26 is selectively removed by etching, and the base region surface is exposed. An emitter pull-out electrode 28 and a base pull-out electrode 29 are formed, and then, a surface-protecting silicon oxide film 30 is formed.

Patent
06 May 1980
TL;DR: In this article, a P-type monocrystal region is selectively turned into porosity by connecting the silicon to a power source while using mononystal silicon as an anode and platinum as a cathode in a hydrofluoric acid liquid.
Abstract: PURPOSE:To easily obtain this substrate body for a semiconductor integrated circuit, by insulating a surface of a P-type semiconductor substrate except P-type semiconductor regions and one portion of the inside when mounting a plurality of the P- type semiconductor regions, which are mutually lnsulated, onto the P-type semiconductor substrate. CONSTITUTION:Masks 71 are selectively formed on a main surface 62 of P-type monocrystal silicon 61, proton ions 73 are injected and proton injecting regions 75 are changed into N-type by thermally treating the silicon at 400-600 deg.C in a nitrogen atmosphere. A P-type monocrystal region 76 is selectively turned into porosity by connecting the silicon 61 to a power source while using monocrystal silicon as an anode and platinum as a cathode in a hydrofluoric acid liquid. Porosity is converted into silicon oxide and the N-type regions into P-type regions by thermally treating the silicon substrate at the temperatures of 900-1100 deg.C in an oxygen atmosphere. This structure is utilized for the preparation, etc. of an N channel MIS field-effect transistor.

01 Jan 1980
TL;DR: In this paper, the authors investigated a wet strip process requiring a LPCVD Si 3 N4 to thermal SiO2 etch rate selectivity of between 1 and 2.
Abstract: Concentrated (49%) aqueous HF and ethylene glycol solutions were investigated for a wet strip process requiring a LPCVD Si 3 N4 to thermal SiO2 etch rate selectivity of between 1 and 2. Si 3 N4 etch rates of higher than 20 nm per minute were also desired in order to obtain high throughputs on the single-wafer spray tool. Water, temperature, and HF concentration were found to play a significant role in defining both the etch rates and etch-rate selectivity of LPCVD Si 3 N4 and thermal SiO2 films. The desired Si 3 N4:SiO2 selectivity was achieved at low HF concentrations; at higher HF concentrations, the selectivity decreased rapidly below 1. Water additions to the system produced similar results. Particulate contamination levels were also significantly reduced when a deionized water rinse was used.

Patent
29 Jan 1980
TL;DR: In this paper, a non-dope multi-crystal silicon thin film on a silicon dispersion layer is formed, and a contact hole is opened to use as an electrode take-out hole.
Abstract: PURPOSE:To improve electrical connection between a base plate and an ohmic electrode by opening a contact hole after completion of formation of a non-dope multi-crystal silicon thin film on a silicon dispersion layer. CONSTITUTION:After completion of formation of a silicon dispersion layer 3, formation of a non-dope multi-crystal silicon thin film 7 is started immediately. A thick silicon oxide film 4 is formed, and a contact hole 5 is opened to be used as an electrode take-out hole. When boring the contact hole 5, etching liquid is not brougt in contact directly with a silicon dispersion layer 3 and a silicon oxide film 2 because of presence of the multi-crystal silicon thin film 7. And therefore, it is possible to prevent formation of a stain film on the surface of the silicon dispersion layer 3. An aluminum soldered layer is formed, and aluminum wirings 6 and 6' are formed by photographic etching.

Patent
26 Apr 1980
TL;DR: In this article, the mixture is secured between the inorganic polymer material such as the oxychloride zirconium, ZrO2, etc., which turns into the glass-type inorganic polymers due to the evaporation of the water content and turns into amorphous Zr O2 at high temperature (about 150 deg.C or more).
Abstract: PURPOSE:To obtain the gas-sensitive and moisture-sensitive element which can detect the presence of the gas as well as the humidity at the room temperature by securing the carrier of the inorganic polymer composed mainly of zirconium for the solid powder. CONSTITUTION:The mixture is secured between the inorganic polymer material such as the oxychloride zirconium, zirconium acetate, etc. which turns into the glass-type inorganic polymer due to the evaporation of the water content and turns into amorphous ZrO2 at high temperature (about 150 deg.C or more) and the solid powder carrier such as the titanium oxide, tin oxide, silicon oxide or the like. Thus the paste-type substance is obtained. Such substance is then formed into the prescribed shape and dried after adding the lead wire and then undergoes the heat treatment ot be formed into the element.