Showing papers on "State (computer science) published in 1968"

The Application of Techniques of Artificial Intelligence to Control System Design

Abstract: Publisher Summary This chapter discusses the applicationof techniquesofartificialintelligence tocontrolsystemdesign Aself-organizingsystemisone whichchangesitsbasic structureas a functionofitsexperienceand/or environment The general aim of a self-organizing system is to evolve toward some desired output state or mode of behavior, in spite of some degree of ignorance of process, inputs, or controls As its structure changes as a function of experience, the self-organizing system can be said to “learn” A controller that is also a self-organizing system is called a “self-organizing controller” Such a controller contains three basic subsystems: (1) sensors, (2) learning network, and (3) a goal circuit The sensors—accelerometers, rate gyros, and horizon scanners—observe the local environment and provide descriptive data to the learning network and the goal circuit The learning network consists of decision elements that operate on data input from the sensors and that render a desirable output response

Single Shift-Register Realizations for Sequential Machines

Abstract: —This paper considers the problem of determining whether a sequential machine, given by its flow table, can be realized in the form of a single binary shift register. One-to-one and many-to-one assignments are considered. Binary partitions are introduced, and shift registers are characterized in terms of binary partitions. An algorithm is given for the determination of the required partitions for a shift-register assignment. Binary set systems are introduced and shift registers are characterized in terms of binary set systems. It is proven that there exists a sequential machine that cannot be realized by a single binary shift register of finite length. Methods for determining the set systems necessary for a single shift-register assignment are given. For machines where every state has two distinct next states, a method is presented whereby a number of machines can be easily eliminated as being not fsr realizable. It is then shown how this can be extended to all machines.

Cultural Contrasts and Similarities Among Five Ethnic Groups in the Nilgiri District, Madras State, India, 1800-1963.

Abstract: The Nilgiri District, east of Calicut, India, is dominated by a higher than 6,000-foot massif commonly called the Nilgiris. The northwestern section of the District extends onto the lower Mysore Plateau and the northern section lies in the Mysore Ditch, a broad valley. This study is a survey of how five ethnic groups, the Badagas, Irulas, Kotas, Kurumbas, and Todas, have interacted with neighbors and utilized landscapes within the Nilgiri District. The historical perspective is employed throughout. The study is based upon an occupance concept in which men are treated as 1) makers of cultural products termed occupance forms, 2) landscape utilizers who alter landscapes to varying degrees, 3) gen­ erators of inter-human economic activities, and 4) employees in economies generated by outsiders to their own small cultures. The outstanding characteristics of resultant dynamic cultural complexes, termed occupance patterns, are described. Because dwellings and temples proved to be particularly useful cultural indicators, they were classified according to exterior characteristics and the func­ tional arrangements of their interiors. It also became necessary to employ an agricultural classification system with the three divisions of dry fields, wet fields, and gardens. Todas living mainly on the northwestern upper Nilgiris are differentiated from the other ethnic groups by their barrel-vauljted,

Variable monitoring system

Abstract: An alarm system for monitoring a large number of variables and for producing a permanent printed record of the exact times when variables changed their state. A scanner counter periodically scans a plurality of annunciator circuits, each of which is associated with a variable. Whenever the scanner locates an annunciator circuit whose state indicates that the associated variable has changed its state since the last scan, the number of the associated variable is retrieved from the scanner counter and the time in seconds and fractions of a second is retrieved from a counter clock. This data and other data is assembled and fed serially into an expandable shift register memory. A teleprinter output logic circuit then retrieves the data from the other end of the expandable memory and feeds it slowly to a teleprinter, along with the time in minutes and hours, and the date in days.

Polylinear Sequential Circuit Realizations of Finite Automata

Abstract: —This paper considers the problem of obtaining realizations of synchronous finite automata from their regular expression specifications. A polylinear sequential circuit realization is defined, and it is proven that every synchronous finite automaton has such a realization. A method is developed for the derivation of a polylinear sequential circuit realization of any automaton specified by a regular expression. The method uses a derivative approach and is applied to the reverse of the given regular expression. As a by-product of developing the method, a connection between the state assigmnent problem and regular expressions is established. Another by-product is a simple method for obtaining polylinear sequential circuit realizations of automata specified by flow tables instead of regular expressions.

Digital System Design Automation—A Method for Designing a Digital System as a Sequential Network System

Abstract: —This paper deals with computer-aided design of digital systems and presents a formal method for designing a digital system via state tables. The steps of the design method can be summarized as follows: a) a system is described by a set of microprograms written in a "transfer language," b) the set of microprograms is translated into a set of flow tables by an algorithm, and c) the flow tables are converted into logical diagrams by synthesis procedures. The purpose of step a) is to aid the designer in describing the system; the result of step b) makes it possible to reduce the logical complexity of the system by using systematic techniques of the sequential network theory; and the result of step c) is a system of interconnected sequential networks, operating simultaneously which may include iterative asynchronous networks.

Unitary Shift-Register Realizations of Sequential Machines

Abstract: —The problem of determining secondary state assignments for sequential machines such that the binary memory elements are connected in the form of shift registers is studied. An algorithm for finding such state assignments is developed. One or more code words may be assigned to a state of the sequential machine. The only restriction is that the realizations be unitary. A single shift-register realization of a sequential machine is unitary if and only if all the code words assigned to a state have the same first digits. A multiple shift-register realization of a sequential machine is unitary if and only if all the code words assigned to a state have l identical digits, where l is the number of shift registers in the realization. With our technique, the unitary realizations with the minimum number of shift registers can be obtained for any finite, deterministic, synchronous, and reduced (minimal-state) sequential machine, each of whose states has a nonempty predecessor set. The algorithm is suitable for programming on digital computers.

High speed digital circuits

Abstract: Apparatus is provided in digital data equipment for transferring a binary signal to a flip-flop, and deriving therefrom a buffered output signal representing the state into which said flip-flop is being switched by anticipation means coupling the input terminal of the flip-flop to a buffer amplifier driven by the flip-flop. A multibranch, multistage selector tree is employed to selectively couple one of a number of binary signals to the flip-flop. The anticipation means and selector tree overcome and minimize the limitations in switching speeds inherent in such apparatus implemented with insulated-gate, field-effect transistors in an integrated circuit. Switching speed of the flip-flop is increased by the combination of (1) a push-pull arrangement such that when a binary signal is applied to one side the complement of the binary signal is applied to the other side, and (2) an anticipation circuit temporarily shunting current around a load resistor in series with a given one of two cross-coupled active elements.

The Application of Shift Registers to Secondary State Assignment: Part II

Abstract: —An algorithm, which determines whether or not an arbitrary sequential machine can be realized using a set of equal-length shift registers, is developed. When realization is possible, a basis for state assignment is also given.

Associative memory circuitry

Abstract: An associative memory cell comprising a memory circuit and an association circuit. The memory circuit includes first and second transistors cross coupled in a bistable circuit configuration so that the first and second transistors alternately conduct as the cell is switched from one to the other of its two stable conductive states. An association current switching circuit is connected between the memory circuit and an associative sense terminal and is further connected to a sense-write circuit. The association circuit is responsive to the conductive state of the memory circuit and to the conductive state of the sense-write circuit to either conduct current from the associative sense terminal or remain nonconductive and thereby indicate association between the sense-write circuit and the memory cell.

Solid state memory and coding system

Abstract: A load sequence controller is provided which takes the form of a system of solid state memory elements, write circuits, interrogators and decoders to perform the function of a step switch which serves to allocate a plurality of loads selectively. The memory elements serve to receive and store an electrical signal representative of one of two binary states. The interrogator, which includes a logic decoder, serves to apply interrogating signals selectively to the memory elements, thereby providing a pattern of output signals representative of the binary state of the received signal for, in turn, energizing the selected loads. A circuit is provided for skipping the interrogating function of at least a selected one of the memories. The skipping circuit is interposed between the decoder output circuit and the memories for receiving the interrogation signals and has an output circuit for routing the interrogation signal on a selected one of the decoder output circuits as an input trigger signal to a counter to change the pattern of count signals quickly for skipping the interrogating function of the memory associated with the selected decoder output circuit.

Circuit for providing nonvolatile memory

Abstract: A bistable flip-flop circuit having a memory core is designed to return to a preferred state after power failure or radiation burst. A feedback loop from the memory core senses whether the preferred state is the same as the state before power failure or radiation and, if not the same, changes the state of the flipflop circuit.

On the Implementation of Failure-Tolerant Counters

Abstract: —A new method of designing and implementing intrinsically failure-tolerant counters with error-correcting state assignments is proposed. Threshold logic elements are used, and state recovery circuitry is united with the flip-flop input logic. A decimal counter built according to this method requires considerably fewer components and has a lower probability of failure at less cost than a diode logic version.

Data processing with dual function logic

Abstract: The contents of a selected one of plural general purpose registers in a data processing system are selectably coupled through first-ZERO-detecting logic to modify the contents of a buffer register. The modification takes the form of setting to the ONE state the bit position in the buffer register corresponding to the low order ZERO position of the originating register contents and resetting any lower bit positions to ZERO. The modified contents of the buffer register are then coupled back to the one originating register. Program-controlled circuits perform, in selectable sequences, the normal store and reset types of operations on the originating registers in the course of the movement of information to the ZERO detecting logic and back again. Illustrative processing functions that can be selected in this fashion include marking a low order ZERO and incrementing the contents of the originating register. Another first-ZEROdetecting logic circuit is employed to control the operation of a rotate circuit in cooperation with the first-mentioned ZERO detecting logic to permit both ZERO detectors to have a data bit width which is much smaller than the processor word size.

A Preliminary Survey of the Avifauna of the Mexican State of Oaxaca. (Volumes 1 and 2).

Abstract: This survey presents separate accounts for the 659 species of birds of undoubted occurrence in Oaxaca and for the 34 species and one hybrid of questionable occurrence. All available information concerning the hypothetical birds is included. For the remaining accounts, information is presented regarding relative abundance, seasonal occurrence, habitat preference, geographical and elevational ranges, and breeding evidence. Some accounts incorporate taxonomic dis­ cussions. All Oaxaca data are given for certain rare birds and for the 75 species for which there are no previous acceptable published records for the state. A new scheme for abbreviated presentation of breeding data is discussed and is used in the species accounts. Chapters are devoted to general physiography and climate. The major avian habitats of Oaxaca are discussed in relation to their distribution, structure, composition, and climate. A map of major habitats is presented. A gazetteer embraces all Oaxaca ornithological localities that have been mentioned in the literature or used on specimen labels. A bibliography of the literature cited in this survey is also given. An analysis of the avifauna lists by habitat the 455 species believed to breed in the state and discusses current

Feasibility study of system state estimation

Abstract: The results of a feasibility study to apply state estimation techniques to an electric power system are summarized. The state estimator is a digital data processing scheme which constitutes the real-time data base from which many of the central control, display, interrogation, monitoring, alarm, and logging functions derive their information. The state estimator, when included in a simulation of the sensing and telemetry subsystems, can also be used off-line to explore the design trade-offs between accuracy and cost of the information subsystem required for power system control.

Retaining wall design-an example of small-scale optimization

Abstract: THE FEASIBILITY OF THE APPLICATION OF OPTIMIZATION TECHNIQUES TO RELATIVELY SMALL CIVIL ENGINEERING PROBLEMS AS TYPIFIED BY RETAINING WALL DESIGN IS PRESENTED. THE OBJECTIVE FUNCTION AS MEASURED BY THE COST OF CONCRETE AND REINFORCING STEEL IS MINIMIZED WITH RESPECT TO THE TOE, HEEL, STEM BASE AND FOOTING THICKNESS DIMENSIONS. FOUR DIFFERENT NUMERICAL SEARCH TECHNIQUES ARE EMPLOYED IN CONJUNCTION WITH A DIGITAL COMPUTER. THEY INCLUDE: AN EXHAUSTIVE SEARCH, THE CONVERGING GRADIENT ASCENT, THE STEEPEST ASCENT AND THE RANDOM SEARCH METHODS. THE RELATIVE EFFICIENCIES OF THE VARIOUS APPROACHES ARE DISCUSSED AND COMPARED. BASED ON COMPUTER RUNNING TIME AND PROGRAMMING EFFORT REQUIRED, IT WOULD APPEAR THAT THE STATE OF THE ART HAS REACHED THE POINT WHERE VERY LITTLE ADDITIONAL EXPENDITURE IS REQUIRED IN ORDER TO OPTIMIZE THE DESIGN OF CERTAIN TYPES OF RELATIVELY SMALL, COMMON CIVIL ENGINEERING PROBLEMS. /AUTHOR/