Showing papers on "Stuck-at fault published in 1969"

Selector circuit for determining faults in polyphase transmission systems

Abstract: The invention provides a selector system for determining which phase or phases of a polyphase power transmission system are affected by a fault. The fault results in a fault current in the affected phase (phase-to-ground fault) or phases (phase-to-phase fault). To distinguish these changes from the existing phase currents due to normal loads, the quantities monitored are stored (phase and amplitude) and any changes in them are inspected to see whether a fault has occurred and, if so, what type of fault it is. Preferably, the ''''phase-to-phase'''' currents are the quantities monitored. The pattern of any substantial changes in these quantities establishes a fault pattern indicative of the nature of the fault. Means may also be provided for following developing faults. A measuring unit may be connected to the appropriate phase or phases following identification of the fault.

Noise discriminating fault apparatus

Abstract: Errors sensed in a data handling system are OR''ed into a latch in a data handling system which handles some number of data words (say 200) serially, a scan of all of the words comprising a frame, errors and faults which may occur at any time, in any word, in any frame, may set a fault latch. However, once set, the fault latch is reset only at the end of every 16 frames. The output of the fault latch is signal-averaged, or integrated, in an RC integrating network having a time constant of between ten and twenty times the period of the sixteen frames of words comprising a fault period. By comparing the average output voltage over a long period of time with a standard voltage, indicative of the average voltage equivalent of an errorindicating duty cycle of the fault latch (in contrast with spurious setting as a result of noise signals), an indication of noise-discriminating fault is achieved.

Fault diagnosis of logical circuits

Abstract: Some new techniques for finding minimal set of tests which detect faults in combinational logic networks are described A systematic procedure which can be programmed on a digital computer is given Moreover, a new approach to the design of fault detection experiments for sequential machines which takes into account the actual construction of the sequential network is described

A method of automatic fault-detection test generation for four-phase MOS LSI circuits

Abstract: To Determine Whether an integrated digital circuit is working properly, one may apply to the circuit a set of well-devised test sequences and compare the resultant outputs with the corresponding correct outputs. Any discrepancies indicate the presence of a fault. The main task here is to find a set of test sequences which can detect the presence of any prescribed fault in the circuit. This test generation problem will become formidable for large scale integrated arrays, since large number of logic circuits may be contained in an array with a limited number of exterior terminals.