Showing papers on "Stuck-at fault published in 1977"

Test generation for large logic networks

Abstract: A system for automatic test pattern generation for large logic networks is described. The network to be tested is assumed to comply with a set of ground rules for testability. The system includes features for automatic subdivision of the network into easily tested sub-networks, automatic test generation programs, and a post-processor which produces a highly efficient test program. Applications to fault diagnosis, and to fast processing of design changes and variations for machine features are considered.

SCIRTSS: A Search System for Sequential Circuit Test Sequences

Abstract: This paper describes SCIRTSS (a sequential circuit test search system). An analytical basis is given for using tree search techniques in determining test sequences for sequential circuits. The basic algorithm for the system of SCIRTSS programs is described and the extent to which the user can influence the search procedure is discussed. Included are the results of the application of SCIRTSS to eight sequential circuits of varying complexity on each one of which it succeeded in finding a fault detection sequence for at least 98 percent of the simple logical faults. This suggests that SCIRTSS can be effective on more complex LSI parts than other automatic test generation methods currently available. Breaking the tree search into two separate search procedures and partitioning circuits when possible into control and data sections are unique features which contribute to SCIRTSS efficiency.

An Algorithm for Testing Random Access Memories

Abstract: This correspondence presents an optimal algorithm to detect any single stuck-at-1 (s-a-1), stuck-at-0 (s-a-0) fault in a random access memory using only the n-bit memory address register input and m-bit memory buffer register input and output lines. It is shown that this algorithm requires 4 X 2nmemory accesses.

Fault tolerant 92160 bit multiphase CCD memory

Abstract: technique in combination with laser burned fuses. During chip test, good and bad blocks are identified and the bad blocks are disconnected from the power supply by laser burned fuses. Each good block has its shorted address line fuse burned out which puts it in series with the othcr good blocks; Figure 2. No special masks are required. The good blocks are linked together by a serial addressing technique. In effect, thc linked blocks can be thought of as bit positions in a shift register such that if a “1” is inserted into the register, it can be shifted thru the register (blocks). Thus, to address a block, the “1” is shifted to the desired block and a common enable line is then activated. Data can then be written or read from the addressed block. Thus, at the system level, it is only necessary to guarantee a certain total number of good blocks to span the address range. No special method of block identification or bookkeeping of parts is required; this simplifies use.

An efficient method of fault simulation for digital circuits modeled from boolean gates and memories

Abstract: The ability to predict the behavior of digital circuits containing faults is required for the verification and automatic generation of fault detection tests, and for the creation of fault dictionaries. The most common method of prediction is with a fault simulation program.Fault simulators simulate the fault-free (good) circuit and each of the possible faulty circuits. In most cases, the faulty circuit is assumed to contain only a single fault modeled as either a component input or output stuck-at-0 (SA0) or stuck-at-1 (SA1). Even so, a typical circuit may imply hundreds to thousands of possible faulty circuits. Reducing the cost of simulating large numbers of faulty circuits is the first major consideration in fault simulation.

Fault Diagnosis of Semiconductor Random Access Memories.

Abstract: : This report deals with the problems of testing semiconductor random access memories and of locating faults on a memory board. Memory test procedures can be divided into three classes, functional testing, pattern sensitivity testing and DC parametric testing. Existing test procedures for testing semiconductor memories are either limited in their fault coverage or require a prohibitive amount of time. A new functional test procedure based on a fault model that takes into account a large variety of faults encountered with semiconductor memories is presented. The fault model is not based on the 'gate' level as in classical fault diagnosis but is formulated on a higher level in terms of functional blocks, like the decoder and the memory cell array. The proposed functional test procedure takes 0(n x log sub 2) units of time where n is the number of words in memory. This gives a dramatic improvement in the testing time required over well-known test procedures line 'galpat' and 'Walking Ones' which take 0(n squared) units of time. Algorithms for the functional test procedure are given. The problem of locating faults on a memory board to memory chips, decoder logic, data registers, and bussing structure is discussed. A test scheme for this problem is given. Finally various test procedures presented in the thesis are evaluated for fault coverage, time requirement and east of implementation.

Maintenance strategies for PCM circuit switching

Abstract: During all the system design phase of an SPC switching system, a considerable effort is devoted to maintenance, both from a hardware and software point of view. The maintenance phases include fault detection, fault analysis (e.g., identification of the faulty security block within the switching system), fault isolation, fault reporting, fault localization, fault clearance, and restoration to service with the eventual requalification and reinitialization of the repaired security block. The paper mainly discusses fault detection and fault analysis strategies with specific reference to PCM digital switching systems. Different means leading to fault detection are presented with reference to central control, network access devices (scanners, drivers, markers), and digital switching network (duplicated or not duplicated). These means include automatic on-line tests (monitoring and routining), on-demand on-line tests, and alarm handling. Fault analysis can be accomplished by means of a deductive or a statistical method. As the latter seems more attractive, three basic methods of statistical fault analysis are presented. They use, respectively, two counters (operation and fault counter) per security block; one fault counter per security block; one "historical" fault stack, in which all the identities of security blocks involved in faulty operations are stored. The above fault analysis strategies are compared mainly in terms of core memory occupancy, processor time, and software complexity.

``On the Analysis of Fault-Trees''-Some Comments

Abstract: Dr. Bennetts is to be complimented for an extremely well written tutorial paper [1] . The first part of [1] describes an algorithm for obtaining a near-minimal s.o.p. expression from topological description of the network using reverse-Polish technique. The second part of [1] describes an algorithm for modifying this s.o.p. expression into another s.o.p expression / \\ each term of which is disjoint with all other terms. Our specific comments are listed here. 1. Work involved in obtaining reverse-Polish expression for primary output of a fault-tree can be considerably reduced by proceeding from bottom to top instead of from top to bottom as suggested in [1, p 177]. Following this procedure the reverse-Polish expression for the primary output of the No fault tree of [1, Fig. 2] can be written by direct inspection asS

Resolution-Oriented Fault Interrelationships in Combinational Logic Networks

Abstract: This correspondence considers fault resolution as a process of applying a sequence of input vectors, called tests, to a combinational logic network in order to resolve an existing fault situation from within a given master set of faults. A functional approach based upon an extension of the well-known Boolean difference concept to fault dependent situations is described. The test sets resulting from this extension, called fault dependent test sets, are fundamental to our considerations and are shown to be obtainable in a straightforward manner from standard test sets. Two fault interrelationships are defined which are particularly relevant to the resolution problem in that they algebraically describe the inherent limitations to the degree to which the existing fault situation can be resolved from within a given master set of faults using algebraic terminal experiments and fault dependent testing. Because these interrelationships are defined from a resolution-oriented point of view, they can be seen to be somewhat more intimate than other fault interrelationships which have been previously described in the literature. Some important ramifications of these interrelationships are discussed.

An advanced automatic test generation system for digital circuits

Abstract: : This is the third and final report documenting our research into the design of a new and powerful automatic test generation system for digital logic, called TEST/80. This system is designed around the following six concepts. 1. A powerful circuit preprocessing analysis which leads to greater efficiency during stimulus generation. 2. An effective initialization algorithm. 3. The use of time frames, phases and periods so that asynchronous circuits can be accurately processed during stimulus generation. 4. The use of functional level primitives so that complex circuits including shift registers, counters and RAM's, can now be effectively processed. 5. The use of a stimulus generation algorithm which incorporates the concepts in 1-4. 6. The use of a functional level concurrent fault simulator, used to grade a test and produce a fault dictionary.

Minimal Fault Tests for Redundant Combinational Networks

Abstract: This correspondence is concerned with the detection of permanent faults in redundant combinational networks. Fault masking in such networks is examined. A method for determining an optimal test set that will detect all detectable faults is given.

Statistical Characterization Of Intermittent Faults In Digital Systems

Abstract: SmMARY In this paper, the problem of characterizing the stochastic behavior of intermittent faults is considered. Three analytical models for intermittent faults in digital systems are discussed. First model assumes that the intermittent faults can be modeled as a renewal process. The second model is a finite-state Narkovmodel. Finally, in the third model the fault-free interval between two intermittent faults is considered and the intermittent fault process is characterized in terms of these fault-free i ntervals. It is expected that these models will find a pplication in the prediction of performance of detection procedures for intermittent faults.

Rapid fault finding tester for TV sets - has identical set as simulator with selective switching and indication of functional modules

Abstract: The fault-finding test jig for colour T.V. servicing comprises a fault simulator using an identical type of set to that under test. Each individual functional module (integrated circuit etc.) of the set under test is also fitted in the simulator (19-24). Each of these modules or groups of modules is wired to a selector and light-emitting diode mimic display panel (26, 27) associated with the control monitor (18). By selectively switching out, or by introduction of simulated fault signals, the fault on the test set can be reproduced on the simulator monitor screen. The light-diode matrix will then indicate on the simulator the module or group responsible for the faulty operation. It is then a simple matter to locate the fault in the set under test.

Maintenance Strategies for PCM Circuit Switching

Abstract: During all the system design phase of an SPC switching system, a considerable effort is devoted to maintenance, both from a hardware and software point of view. The maintenance phases mdude fault detection, fault analysis (eg., identification of the faulty security Mock within the switching system), fault isohtion, fault reporthg, fault localization, fault clearance, and restoration to with the eventual reqdificabion and reinitializa- tion of the repaired security Mock. The paper mainly discusses fault detection and fault analysis strategies with specific reference to F" digital switching systems. Different means leading to fault detection are. presented with refer- ence to central control, network access devices (scanners, drivers, markers), and digital switching network (duplicated or not duplicated). These means include automatic on-line tests (monitoring and routin- in&, on-demand on-line tests, and alvm handling. Fault analysis can be accomplished by means of a deductive or a statistical method. As the latter seems more attractive, three basic methods of statistical fault analysis are presented. They use, respec- tively,

Synthesis of Optimal Ambiguity Resolver Functions

Abstract: Large-scale integration (LSI) circuits impose particular constraints and present special opportunities for improving the diagnostic resolution of a digital system. In particular, bond failures represent a very significant failure mode in integrated circuits, so it is important to be able to identify a fault on an input/output lead to a single bus of a least replaceable unit, and it is desirable to do this using a minimum number of test points.

Fault location in Reed-Muller canonic networks

Abstract: In the paper, single and multiple-fault locating test sets for Reed-Muller canonic networks are derived The fault model assumes stuck-at faults at the I/O leads of AND gates, and that an EOR gate under a fault can produce any other function of two inputs other than equivalence The results in the paper give an insight into the complexity of testing of a class of logic networks