Showing papers on "Synchronizer published in 1974"

Synchronization system for a combined cycle electric power plant

Abstract: A combined cycle electric power plant includes gas and steam turbines and steam generators and a digital/analog control system. In the control system, an automatic digital computer control generates position setpoints for the gas turbine fuel valves and the steam turbine inlet valves to control speed and load. A synchronizer system includes a sequencer which is largely embodied in the digital computer as an element of the automatic control and it further includes a synchronizer which is external to the automatic control. The sequencer connects the synchronizer to synchronize the three generators in a sequence which depends on the startup and loading operation of the turbines, the synchronization operation of the synchronizer and the operation of the breakers. Turbine speed changes are initiated by the speed/load control under synchronizer control.

Synchronizing device for gear couplings in change-speed gears

Abstract: Synchronizer for jaw tooth clutch means in change-speed gearing. In a cone-type synchronizer positioned between a pair of gears selectively connectible by jaw tooth clutches to a shaft it has been found that the axial length thereof can be shortened with adequate operational capacity maintained if the ratio between the maximum diameter (D) of the external cone bears to the axial distance (A) between the remote faces of the internal cone a ratio greater than the integer 3. Optimum operation is achieved if the ratio (D:A) is between 3.4 and 4.0.

Data synchronizing systems

Abstract: A bit synchronizer system is disclosed which is adaptive to varying input conditions such as noise and jitter of data signals particularly PCM telemetry signals. The signal to noise parameter of the input data signal is obtained from a matched filter having a response matched to signals which are orthogonal to the input data signal. This matched filter also detects transitions in the input data signal which are used to lock a phse locked loop. The loop generates a local clock which is synchronous with the incoming data and can be applied to detect the incoming data bits and reconstruct them into noise and jitter-free output data. Control signals are also extracted from the loop which represent the jitter (viz., the rate of change of the phase) of the input signal. The bandwidth of the loop is varied in accordance with the jitter and noise to signal parameters to the optimum bandwidth for the prevailing noise to signal ratio and jitter on the incoming data signal.

Manual/automatic system for synchronizing multiple turbines in a combined cycle electric power plant

Abstract: A combined cycle electric power plant includes gas and steam turbines and steam generators and a digital/analog control system. In the control system, an automatic digital computer control generates position setpoints for the gas turbine fuel valves and the steam turbine inlet valves to control turbine speed and load. A synchronizer system includes an automatic synchronizer subsystem and a manual synchronizer subsystem. The automatic synchronizer subsystem includes a sequencer which is largely embodied in the digital computer and it further includes a synchronizer which is external to the automatic control. The automatic sequencer connects the synchronizer to synchronize the three generators in a sequence which depends on the startup and loading operation of the turbines, the synchronization operation of the synchronizer and the operation of the breakers. The manual synchronizer subsystem responds to operator inputs to generate a speed reference for the synchronization of each turbine. The synchronization system further includes logic structure needed to permit synchronization to occur and to define the synchronization mode. Turbine speed changes are initiated by the speed/load control under synchronizer system control.

Digital computer system and method for operating a steam turbine with efficient control mode selection

Abstract: A control system for a steam turbine includes an operator's panel and a programmed digital computer which generates valve position signals for the turbine throttle and governor valves. Mode select signals are generated at the panel and the computer includes a mode selector which provides for structuring the control system to implement external synchronizer, load runback, automatic turbine startup, operator automatic, manual and other mode selections.

An automatic synchronizer for suspension culture of L5178Y cells.

Abstract: The excess thymidine-colcemid synchronization method for mouse leukemia L5178Y was automated by deleting the removal of excess thymidine. The synchronizer adds thymidine and colcemid at predetermined times and makes the population accumulated at mitosis available at a designated time. The apparatus is inexpensive to build, easily operated and applicable to large volumes of a static suspension culture.

Circuit for converting an asynchronous signal with a long transition time to a synchronized signal

Abstract: A synchronizer circuit comprises a Schmitt trigger circuit which sharpens the rise or fall of an asynchronous input signal, and a clocked flip-flop circuit which converts the asynchronous signal having the sharpened waveform into a synchronous signal. In another embodiment, complementary asynchronous input signals having a large transition time are supplied to an RS flip-flop circuit in a first repeated interval in synchronism with a first clock pulse. Then, the state of the flip-flop is caused to remain stable in the other intervals. Subsequently, the output of the flip-flop is read out in synchronism with a second clock pulse by a transfer-gate field effect transistor. Thus, the asynchronous input signal is converted to a waveform-shaped and synchronized signal.

Asynchronous, multiplexing, single line transmission and recovery data system

Abstract: Asynchronously multiplexed sample data sub-systems employ transmission over a single line to a remote synchronizer and demultiplexer At the remote synchronizer, the data is recovered by synchronizing signals derived from the data itself A sub-system, or satellite location, supplies continuously sampled binary data along with a satellite identification and synchronizing sequence as a satellite message frame This information is supplied bit-serially, to a multiplexer junction The multiplexed satellite information is delivered asynchronously onto a single line transmission channel with other like bit serial satellite message information from other satellite monitoring sites Such satellite information is transmitted to a central collection and analysis site where it is demultiplexed according to the words and bits that make up a satellite message frame At least two message frames from each satellite monitoring site are always placed on the single transmission channel as a single block of data for that satellite This technique, at the demultiplexer, assures proper recognition of a desired message frame based upon a comparison of satellite identification sequences and a frame synchronization sequence

Adaptive phase synchronizer

Abstract: An adaptive phase synchronizer for synchronizing the phase of received digital data with the phase of a local clock include means for taking multiple samples of each bit of the received data, modulo 2 adders and up-down counters for locating the transitions in the data bits, and phase correcting means responsive to said transitions for adjusting the phase of the data over a range in excess of one bit intervals in accordance with the locations of the transitions in the received data relative to the local clock pulses. Means are provided for rendering the phase correcting means non-responsive to the transitions in the data when more or less than one transition per bit occurs.

Two-phase MOS synchronizer

Abstract: An MOS circuit synchronizes an asynchronous input signal to first and second alternating clock pulses in an integrated circuit system employing clocked ratio logic. A bistable device, such as a flip-flop, has first and second complementary inputs for establishing the state of the device and an output reflecting the state of the device. An input circuit for the bistable device receives the asynchronous signal and applies the signal to the first complementary input and the inverted asynchronous signal to the second complementary input. In addition, the input circuit has gate logic, implemented with field effect transistors, which decouples the asynchronous input for all intervals of time except during the interval of the first clock pulse. An output circuit for the bistable device employs an inverter in series with a field effect transistor which is driven into condition only during the interval of the second clock pulse. The MOS synchronizer circuit thus insures that an output signal of usable logic level is generated for an input signal occuring at any time with respect to the clock pulses of a clocked ratio MOS system.

An all-digital Manchester symbol synchronizer for Space Shuttle

Abstract: The Shuttle S-Band relay communications links via TDRS are coded and may operate at symbol signal-to-noise ratios (Es/No) as low as -5dB. A brass-board all-digital bit synchronizer with very low (0.05dB) degradation relative to an idealized analog model has been designed to process the 216 KBPS Manchester data symbols. This all-digital bit synchronizer, which provides soft decision detected outputs to a convolutional decoder, may be operated at any rate below 216 KBPS by merely changing the master clock frequency.

Digital run length synchronizer

Abstract: Apparatus and method for synchronizing run lengths in a twolevel digital facsimile system. A reversible counter is pulsed at a multiple of the system clock rate, the up count being started upon the occurrence of binary one information and stopped after reaching a predetermined count upon the occurrence of a system clock pulse. This system clock pulse is utilized to provide a binary one output signal. On a transition of the input signal to a binary zero state, the reversible counter is switched to its countdown state. After reaching the predetermined count, the following system clock pulse is utilized to change the output to the binary zero state. This eliminates variations in run lengths which occur when transitions have different phases with respect to the system clock.

Synchronizer system for a motion picture sound recorder

Abstract: The invention is directed to a synchronizer for a sound and motion picture recording system utilizing separate sound and motion picture apparatus In a sound motion picture system, the synchronizer operates to generate a driving voltage for the sound recorder motor, which is representative of the phase difference between synchronizing (sync) signals derived from the motion picture camera and reference signals which are derived from the sound recorder A phase locked system is provided which matches the sync and reference signals and thereby synchronizes or matches the sound recorder to the sync signals

Designing synchronous circuits with partial asynchronous operation using clocked flip-flops with d.c. inputs

Abstract: A practical design technique is developed that takes advantage of four inputs, J, K, S and R, often available on flip-flops to design circuits involving both synchronous and asynchronous behaviour. A compact state-table representation is described, along with the requirements for state reduction, assignment and circuit realisation. The technique can produce a saving in logic complexity over completely asynchronous designs.

Every Finite-State Machine can be Simulated (Realized) by a Synchronous (Asynchronous) Binary Feedback Shift-Register Machine

Abstract: A theoretical model of a microprogram unit is formulated, and the relationship of this model to a form of feedback shift register is developed. The feedback shift-register machine variant has synchronous and asynchronous prototypes. The asynchronous binary feedback shift-register machines realize every fundamental mode asynchronous sequential (finite-state) machine. The synchronous feedback shift-register machine differs from the standard definition by the addition of transitional states to the usual (nontransitional) states, and a single step in the simulation is a move between nontransitional states. When synchronous feedback shift-register machines are generalized in this way, they also become universal components capable of simulating ali finite-state machines.

Solid state synchronizer system which uses the zero crossing point of a syncro output as a reference

Abstract: A synchronizer system where a positioned synchro transmitter has a rotor excited from an a.c. source and a demodulator operating by momentarily sampling the output of the transmitter once every n cycles of the voltage from the a.c. source where n is greater than 1. An integrator is responsive to the pulsed output of the demodulator with a feedback network responsive to the integrator for controlling the instant of sampling the output to null the output voltage. The integrator may be latched at any phase angle thereafter to cause production of an error signal from the demodulator proportional to further relative rotation in the transmitter.

Shuttle bit rate synchronizer

Abstract: A shuttle bit rate synchronizer brassboard unit was designed, fabricated, and tested, which meets or exceeds the contractual specifications. The bit rate synchronizer operates at signal-to-noise ratios (in a bit rate bandwidth) down to -5 dB while exhibiting less than 0.6 dB bit error rate degradation. The mean acquisition time was measured to be less than 2 seconds. The synchronizer is designed around a digital data transition tracking loop whose phase and data detectors are integrate-and-dump filters matched to the Manchester encoded bits specified. It meets the reliability (no adjustments or tweaking) and versatility (multiple bit rates) of the shuttle S-band communication system through an implementation which is all digital after the initial stage of analog AGC and A/D conversion.

A New Concept of Truck Transmission Design

Abstract: The object of this paper is to re-assess the existing principles used in the design of synchronized mechanical transmissions from the point of view of synchronizer duty. By a logical approach, when the main emphasis is given to synchronizer duty, a new transmission concept, known as the ‘M’ series, has been evolved, which brings with it some important advantages: saving of weight; faster synchronization, making for greater road safety; less space; lower manufacturing costs.The theoretical study compares the expected performance with that of a conventional five-speed synchronized transmission under identical conditions. Laboratory and road tests have established the validity of the theoretical appraisal.

Electromagnetic coupling for an altimeter

Abstract: A synchronizer for coupling a corrective servo mechanism to a pneumatic altitude sensor in an aircraft to provide a display with a positive pressure altitude indication. The synchronizer has a first rotor retained on a shaft with gear teeth that are positively engaged with the servomotor. The synchronizer has a second rotor concentric to said first rotor with gear teeth that positively engage the altitude sensor. A coil in the synchronizer is energized and lines of magnetic flux developed which pass through poles in the first and second rotor. An altitude computing device connected to the altitude sensor computes an electrical error signal which activates the servomotor. With the servomotor activated the first rotor is moved. The magnetic attraction between the poles correspondingly causes the second rotor to move and exert a modifying force on the output from the altitude sensor to establish the true pressure altitude output for operating an indicator.