Showing papers on "System bus published in 1973"

Dual computer system with signal exchange system

Abstract: A dual computer system of the type comprising two simultaneously operating central processors is disclosed. The two central processors are connected to each other for processing a breakdown cycle by way of an memory bus exchanger (MBEX) for switching connections between two memory buses, a data bus exchanger (DBEX) for switching connections between the input/output signal lines of the two central processors (CP) and the data bus line, and a dual control unit (DCU) for monitoring the two central processors and controlling the MBEX and the DBEX and thus integrally controlling the dual system.

Patient monitoring and data processing system

Abstract: A physiological monitoring system for use with patients who are critically ill utilizes a system structure which is inherently modular, easily expandable, computer compatible, and ''''fail soft''''. The system is composed of bedside units, central station units and a central processing unit. Patient information such as dynamic waveforms, derived physiological parameters, physiological alarms, trend graphs and multi-parameter plots are provided in addition to such system information as alarm limits and system alarms. The system structure is based upon use of digital data buses which interconnect the units located at the bedside, central station and central processor. The digital data buses provide two-way communication between the system units and yet have a relatively small number of conductors for the amount of information exchanged between the units. The digital data buses are operated in a synchronous mode wherein data words appear on the buses in a predetermined time relationship relative to repetitive synchronizing pulses. Both the transmitter which is generating a given data word on a given data bus and all intended receivers of the data, access that given data word simultaneously after each has counted the same number of intervals from the synchronizing pulse to the predetermined time slot.

Asynchronous communication bus

Abstract: An asynchronous bus for self-determined priority of communication among master computer devices communicating with slave devices through said bus where a multi bit data channel and a multi bit address channel are shared between all of said devices. A logic circuit in each said master device is connected to each of three signal lines common to all logic circuits in all of said master devices. One of the three lines is connected in series in the order of assigned priority between master devices. Means are provided to actuate the logic circuits via the three signal lines to limit access to said bus in the order of assigned priority and to signal to other master units bus availability and to transmit an access granted signal to master units down stream of a user unit with only one logic gate delay per downstream unit.

General purpose digital processor for terminal devices

Abstract: A digital processor includes: a main read only memory store providing instruction and constant data signals; a random access memory store for storing variable data signals; an input/output port unit communicating with the terminal devices; an interrupt address generator controlling the interrupt priority for the terminal devices; an arithmetic and logical unit; an instruction decoding and execution unit controlled according to instructions in a fast access read only memory store address controlled by the instruction signals in the main read only memory store for controlling the operations of the digital processor; and a group of working and general registers for buffer storage of digital signals. Interconnections between the units of the processor are through a single bidirectional data bus. Process steps control the operation of the processor according to an instruction format.

Data storage system with deferred error detection

Abstract: Disclosed is a data transfer mechanism between the data bus of a data processing system and a data store. The data transfer mechanism includes common logic for converting between parity coded data on the data bus and error checking and correcting (ECC) coded data associated with the data store. Parity errors in data for presentation to the data store are detected, and single error correction and double error detection (SEC/DEC) syndrome bits are generated from the original ECC bits when data is to be read from the store and presented to the data bus. Additional circuitry is included to cause a signal indicating a single parity error on the data bus to modify the ECC bits generated for presentation to the data store with the data. On a subsequent read of the data from the data store, the modified ECC bits will produce a set of syndrome bits, specially recognized, to cause the data to be presented to the data bus with the original byte parity error recreated for subsequent detection.

Data-transmission apparatus

Abstract: In a system wherein plural data-handling modules are connectable to time-share a data bus, determination of which module may control the bus at any given instant is made by a plurality of simple conflict-resolving circuits which are associated with respective modules so as to allow economical expansion of the data-handling system. If two modules request control while a third module is using the bus, a decision is immediately made as to which of the two modules will be the next to be given control of the bus.

Access circuit for central processors of digital communication system

Abstract: Maintenance access circuits (MAC) are provided in each of two copies of a programmable Central Processor. The MAC for the active Central Processor is the only one responsive to and capable of executing maintenance instructions. In response to such instructions, the MAC reads information at sense points and controls the state of circuits at control points in both copies of the Central Processor. Program access to information via MAC is independent of which CP is active-that is, the programs which use MAC instructions merely identify the desired CP as active or passive, and the system will respond whether CP phi or CP1 is active. The MAC circuits of each CP communicate with each other by means of an external AC bus system including a select or address bus, a data bus and a return bus. Each MAC has internal maintenance buses corresponding to and in communication with these external buses for transmitting information to control points and for retrieving information from the sense points which are addressed. Addressing is accomplished by an X and Y coincident select codes wherein one of the selection codes, namely the Y-select code is selectively gated to the external MAC Select Bus in such a manner that any one of the following combinations of Central Processor may be addressed: only the active CP, only the standby CP, or both active and standby CP''s.

Computing system bus

Abstract: A single parallel bus interconnects the various portions of a central processing unit. Data transmission between the various portions of the processor is based on sequential use of the common bus, and is synchronized by control circuitry. Circuit means are included for providing access of the various portions of the processor to the bus, and includes means for generating data on the bus for transmission, and for detecting data transmitted by the bus. To minimize access time to the bus whenever data is to be transmitted, means are provided for precharging the bus to a reference potential and then selectively discharging the bus to correspond to the data to be transmitted. In a different aspect of the invention a common bus is used to transmit data between the processor and computing equipment separate from the processor. In this aspect of the invention, circuitry is provided for detecting current on the bus corresponding to data, and for amplifying this current to a suitable level, and then generating a voltage suitable for transmission by the bus.

Computer processor register and bus arrangement

Abstract: The computer processor comprises a plurality of registers and an arithmetic logic unit along with interfaces with other units of a data processing system connected as sources and sinks to one data bus and one address bus Each source for a bus has leads from the output of a register or a set of interface leads connected to inputs of AND function gates with the gates for a selected source enabled by a control signal, and the outputs of the respective bits of the AND gates of the several sources are connected to OR function gates, the outputs of which comprise the bus A register or set of interface leads acting as a sink has the bus connected to the inputs of AND function gates whose outputs are connected to the inputs of the register or interface leads, and the gates for a sink are enabled by a sink select signal Each of the buses also has its leads connected back as source leads to AND function gates which are enabled by a LATCH signal, thereby effectively making the bus act as a register For certain instructions of the order set, either or both buses may be latched during the processing to retain information while the source register is used for other purposes

Communication switching system with modular organization and bus

Abstract: The system has duplicate central processors, each having its own bus. Subsystem modules include program memory, data base memory, status detector, register-senders, markers, etc., each having one or more memory word stores. Bus interface units of identical construction are interposed between the subsystem modules and the busses. Some modules such as program memory are duplicated and each connected to one bus, while others are connected via their interface unit to both busses. All memory addresses are accessed from a processor via its bus, each address being effective to select only one interface unit, and the complete address being then passed to the subsystem module to read or write a data word.

Computing with multiple microprocessors

Abstract: Computer systems with multiple processors are becoming more common for reasons of reliability and modularity. The use of asynchronous processors, however, leads to problems of complexity of control and of programming. This work investigates the application of multiple asynchronous processors to the computing task at the lowest level - that of interpreting single machine-language instructions. A particular computer configuration with 15 identical processors has been constructed using an interpretive simulator. The processors are of relatively low computing capacity. A common data bus connects the processors with each other and with the main memory. A restriction on the logical connections between processors allows each one to communicate with no more than 2 others, in a chain-like arrangement. Three examples - 2 sort instructions and a matrix multiply - were coded for this machine and run using the simulator. By varying the bus cycle time, it was concluded that adequate support of up to 15 processors can be provided by a common bus with cycle time equal to the processor cycle time. The amount of parallelism achieved was significant but showed dependence on hard-ware parameters and on the algorithm implementations. Direct simulation the computer, with an execution trace of the running system, has yielded some glimpses of how restriction of bus capacity can cause deterioration of the program execution efficiency and amount of parallelism. A simple economic model of a multiple processor system is developed and applied to the 3 examples. The result shows that the minimum cost per throughout occurs with 4,11, and !5 processors, respectively, for the 3 examples when the cost of a processor is i/i0 of the system cost.

Maintenance control arrangement employing data lines for transmitting control signals to effect maintenance functions

Abstract: A maintenance control arrangement for use with a communication switching system having a central processor and a register sender interconnected by a data bus includes a maintenance circuit having direct control latch circuits and gate circuits operable when enabled to provide control signals for controlling apparatus associated with the register sender. A register sender memory stores direct control data bits which indicate which of the direct control latch and gate circuits are to be enabled and a control pulse directive transmitted over the data bus from the central processor to the maintenance circuit effects the generation of enabling signals which upon coincidence with direct control data bits read out of the register sender memory cause selective ones of the direct control latch and gate circuits to be enabled.

I.U. Accelerator Control System Digital Multiplexer

Abstract: A digital distribution system has been constructed at the Indiana University cyclotron facility to link the control computer, an XDS Sigma 2, with the three stages of the accelerator and the control console. This system consists of a network of modular digital multiplexers attached to a common bidirectional data bus. When fully expanded, the system can transmit or receive 16-bit data words to or from 1024 different devices. In addition, a device may generate a computer interrupt by raising 1 of 256 available status bits. The multiplex system was implemented with XDS T series modules and thus is compatible with any DTL or TTL logic.