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Showing papers on "Task (computing) published in 1977"


Proceedings Article
Warren Teitelman1
22 Aug 1977
TL;DR: The system described in this paper makes extensive use of a bit map display and pointing device (a mouse) to significantly enrich the user's interactions with the system, and to provide capabilities not possible with terminals that essentially emulate hard copy devices.
Abstract: This paper continues and extends previous work by the author in developing systems which provide the user with various forms of explicit and implicit assistance, and in general cooperate with the user in the development of his programs. The system described in this paper makes extensive use of a bit map display and pointing device (a mouse) to significantly enrich the user's interactions with the system, and to provide capabilities not possible with terminals that essentially emulate hard copy devices. For example, any text that is displayed on the screen can be pointed at and treated as input, exactly as though it were typed, i.e., the user can say use this expression or that value, and then simply point. The user views his programming environment through a collection of display windows, each of which corresponds to a different task or context. The user can manipulate the windows, or the contents of a particular window, by a combination of keyboard inputs or pointing operations. The technique of using different windows for different tasks makes it easy for the user to manage several simultaneous tasks and contexts, e.g., defining programs, testing programs, editing, asking the system for assistance, sending and receiving messages, etc and to switch back and forth between these tasks at his convenience.

134 citations


Patent
03 Jan 1977
TL;DR: In this paper, a fail-operative automatic flight control system with a totally monitored digital computer for operating upon sensor input data to provide command signals to the aircraft surface control actuators is described.
Abstract: A dual channel, fail-operative automatic flight control system is disclosed in which each channel includes a totally monitored digital computer for operating upon sensor input data to provide command signals to the aircraft surface control actuators. The operative program for each computer is repetitively executed to effectively provide continuous control. The program is organized into a plurality of tasks to be performed by the computer with program segments associated with the respective tasks and a program routine for determining that all of the tasks have been completed for each program iteration. If non-completion of a task is detected, the program enters a failure routine which stops execution of the program. The program also includes a routine for generating a dynamically varying pattern in accordance with the continuously reiterated execution of the program. The system includes a detector for determining that the correct pattern is being generated and shuts down the system upon detecting a failure of the computer to generate the correct pattern. All of the instructions of the computer instruction repertoire operatively utilized in the system are employed to control the program flow whereby failure of an instruction to operate properly will cause the program to flow into an abnormal path thus causing the task completion program routine to indicate failure and stop the computer. Additionally, the system utilizes further techniques such as dual data and program memory banks to perform redundant computations, all of the techniques in combination providing an automatic flight control system with two autonomous fail-passive channels, the two channels providing a fail-operative system.

51 citations


Patent
Rudolf Kober1
12 Sep 1977
TL;DR: In this article, a distributed computing system has a data exchange processor which is adapted to control operations involving the transfer of data among components of the distributed computing systems, whereby the master computer is spared the task of controlling data transfer operations.
Abstract: A distributed computing system has a data exchange processor which is especially adapted to control operations involving the transfer of data among components of the distributed computing system, whereby the master computer is spared the task of controlling data transfer operations.

49 citations


Patent
14 Mar 1977
TL;DR: In this paper, a method of operating a data processing system having at least two real-time data processors is described, where each processor is assigned a predetermined upper limit value for its utilization ratio, which value lies below the processor's overload limit.
Abstract: A method of operating a data processing system having at least two real-time data processors is described. The method permits the processing of tasks with minimal delay. Given tasks may be coupled to one of the data processors, depending on the type of task and which of the processors has been preselected to operate on such tasks. Each of the data processors is continuously monitored for the purpose of continually determining the utilization ratio for each processor. Each processor is assigned a predetermined upper limit value for its utilization ratio, which value lies below the processor's overload limit. If the upper limit value is exceeded, tasks coupled to one data processor are diverted to another data processor. In the other processor the diverted tasks are processed after the program switchover.

38 citations


Patent
Roever Paul Rudolf1
11 Oct 1977
TL;DR: In this paper, the wait relations among N tasks in a multiprocessing, multiprogramming CPU environment are conformed to a vector of N+1 fields recording which tasks in the system are active and upon what other task any given task directly waits.
Abstract: The wait relations among N tasks in a multiprocessing, multiprogramming CPU environment are conformed to a vector of N+1 fields recording which tasks in a system are active and upon what other task any given task directly waits. The vector may be stored in a global register. Positions 1 through N are assigned to the N tasks such that a value p in position r means that task r is waiting directly on task p. One value j of the possible values 0,1,2, . . . , N+1 is designated to indicate an active task. Position j always shows the value j. Without loss of generality and to facilitate the discussion j is assumed to be 0. Thus, the value 0 in register position r means that task r is not waiting and position 0 always has the value 0. The presence of any deadlocks (closures) among the wait relations can always be detected by the computing system by making repeated translations of the vector fields within and upon themselves in no more than log 2 (N+1) iterations. In this regard, log 2 (N+1) denotes the smallest integer equal to or greater than the base 2 logarithm. The translation of fields within and upon themselves means that for each global register position r containing pointer p, then the contents g of register position p are substituted as the new contents of position r for the iteration 0≦r, p, g≦N.

33 citations


Patent
11 Nov 1977
TL;DR: A teaching machine for studying foreign and native languages comprises a task unit for a program of successive algorithmic exercises having unambiguous solutions, a machine control unit, answer input unit, an input answer analysing unit, a signalling unit, reference unit and a decoder as mentioned in this paper.
Abstract: A teaching machine for studying foreign and native languages comprises a task unit for a program of successive algorithmic exercises having unambiguous solutions, a machine control unit, an answer input unit, an input answer analysing unit, a signalling unit, a reference unit and a decoder. The task setting unit is provided with a detachable programmer made as a memory interacting with a memory unit of the task unit and the answer input unit and thus ensuring programming of any algorithmic exercise from any conventional textbook. The proposed invention permits wider didactic machine capabilities and its more economic operation.

17 citations


Patent
Charles P. Thacker1
16 Feb 1977
TL;DR: In this paper, a data processing apparatus for processing digital data in accordance with a plurality of predetermined tasks of preassigned priority values and identified by a respective plurality of devices connected to the data processing infrastructure is described.
Abstract: A data processing apparatus for processing digital data in accordance with a plurality of predetermined tasks of preassigned priority values and identified by a respective plurality of devices connected to the data processing apparatus. Each device is capable of generating the respective task request signal when requiring service by the data processing apparatus. The data processing apparatus includes a first memory for storing a plurality of executable instructions, a second memory for storing addresses of locations in the first memory, a priority determining device responsive to the task request signals for generating a control signal indicative of the task request signal having the highest current priority value, and an addressing device responsive to the control signal for providing an address to the second memory, the addressed location in the second memory containing the next address of the first memory to be accessed for continuation of the processing of the requesting task and thus servicing of the respective device, wherein said next address is a part of an executed instruction.

16 citations


Proceedings ArticleDOI
01 Jan 1977
TL;DR: A collection of queueing network models with distinguishable tasks in the system is developed and solved to represent various aspects of a multiprogrammed computer system.
Abstract: A collection of queueing network models with distinguishable tasks in the system is developed and solved to represent various aspects of a multiprogrammed computer system. The basic model is a closed queueing network which models a system with a multilevel memory hierarchy with distinguishable tasks in the system. Equations which describe the behavior of the system are solved analytically. Using the solution of these equations, various performance measures-processor utilization, queue lengths, rate of task execution, expressions for system overhead, and effective CPU utilization - are developed.Program behavior is characterized by CPU processing, page faults, and I/O processing with the possibility of queueing delays. System behavior is characterized by considering the processing requests of all jobs in the system. The solution technique is one which equates the rate at which a job of a particular class enters each queue to the rate at which a job of a particular class leaves that queue.

1 citations