Showing papers on "Thin-film transistor published in 1974"

Insulated-gate thin film transistor with low leakage current

Abstract: An insulated-gate thin film transistor is provided with low leakage drain current. A second semiconductor layer makes contact with the source electrode and the semiconductor layer forming the channel of the transistor at least between the source and drain electrodes. The second semiconductor layer is of opposite type conductivity from the channel semiconductor layer and preferably forms a PN heterojunction with the channel semiconductor layer. Alternatively, a metal layer may be used in place of the second semiconductor to form a Schottky-barrier junction with the channel semiconductor layer instead of a PN junction. Preferably, the channel semiconductor layer and the second semiconductor layer or the metal layer are sequentially evaporation deposited through the same deposition mask onto a substrate from evaporant sources spaced substantially different distances from the substrate so that the sequential layers are deposited on first and second overlapping areas of the substrate.

SOS Bipolar transistor

Abstract: A planar bipolar transistor is made by the successive ion implantations of selected atoms into selected regions of a layer of doped single-crystal silicon on an insulating substrate, such as sapphire or spinel. The silicon layer is epitaxially grown, has a thickness of between 0.5 and 5 μm, and is formed in two strata of different resistivities. A collector contact well is ion implanted into the upper stratum and annealed to diffuse it into the lower stratum of lower resistivity. The transistor is isolated, as a mesa, on the substrate; and an edge-guard region is ion implanted through the periphery of the mesa, except in the region of the emitter-base junction.

Integrated circuit and method for fabrication thereof

Abstract: An integrated transistor circuit arrangement provides a multicollector transistor with Schottky diodes and ohmic connections selectively formed at the collector terminals. In the illustrative example, a vertical transistor is formed in an N-type epitaxial layer overlying an N+ substrate. A through-extending region of P+ material encircles the region of the epitaxial layer in which the vertical transistor is formed. The base of the vertical transistor is formed by the implanting of P-type impurity in a location spaced apart from the surfaces of the epitaxial layer. The resulting base has a symmetrical profile relative to the faces of the epitaxial layer. Therefore, the transistor may be operated with the collector at the surface without penalty of electrical operation. In the illustrative example, a PNP lateral transistor is utilized as a current source for the vertical transistor.

Improved stability in PbS/Al 2 O 3 thin-film transistors

Abstract: Insulated-gate field-effect-transistor structures , prepared with thin films of lead sulfide as the semiconductor and aluminum oxide as the gate insulator, exhibit greatly improved stability with regard to carrier-trapping effects as compared with other thin-film transistors (TFTs) such as those made of cadmium selenide. The devices are prepared in a series of additive evaporation steps (through stencil masks) in a single pumpdown of the vacuum system. They are n-type but exhibit field-effect inversion to p-type. They are generally enhancement devices but can also be prepared as depletion devices by increasing the time and temperature of the postdeposition anneal. The carrier mobility is of the order of 10 cm2/V-sec, and the carrier concentration is approximately 3 × 1017/cm3.