Showing papers on "Twiddle factor published in 1987"

Real-valued fast Fourier transform algorithms

Abstract: This tutorial paper describes the methods for constructing fast algorithms for the computation of the discrete Fourier transform (DFT) of a real-valued series. The application of these ideas to all the major fast Fourier transform (FFT) algorithms is discussed, and the various algorithms are compared. We present a new implementation of the real-valued split-radix FFT, an algorithm that uses fewer operations than any other real-valued power-of-2-length FFT. We also compare the performance of inherently real-valued transform algorithms such as the fast Hartley transform (FHT) and the fast cosine transform (FCT) to real-valued FFT algorithms for the computation of power spectra and cyclic convolutions. Comparisons of these techniques reveal that the alternative techniques always require more additions than a method based on a real-valued FFT algorithm and result in computer code of equal or greater length and complexity.

The re-discovery of the fast Fourier transform algorithm

Abstract: The discovery of the fast Fourier transform (FFT) algorithm and the subsequent development of algorithmic and numerical methods based on it have had an enormous impact on the ability of computers to process digital representations of signals, or functions. At first, the FFT was regarded as entirely new. However, attention and wide publicity led to an unfolding of its pre-electronic computer history going back to Gauss. The present paper describes the author's own involvement and experience with the FFT algorithm.

A unified approach to the fast computation of all discrete trigonometric transforms

Abstract: A new approach is developed for the fast computation and VLSI implementation of all discrete trigonometric transforms in the least number of operations and pipelining stages. This is achieved in terms of the fast algorithm (FRFT) for the real discrete Fourier transform. FRFT is based upon Givens' plane rotation as the basic unit of computation in contrast to FFT's which are based upon the complex butterfly.

The decomposition of long FFT's for high throughput implementation

Abstract: One of the major limiting factors in high throughput FFT systems implementation is the bus bandwidth. The data traffic over the bus consists of 3 types: input/output data, exponential coefficients (W factors) and instruction code (for the executing processor). Reduction of the bus load requires employment of a dedicated processor with internal memory and LUT (for the W factors) that will be able to compute certain sized FFT modules. Computation of larger sized FFT's using these smaller sized modules then requires support by an external LUT. Minimization of this LUT size and the bus load effect of the twiddle factor introduction can be achieved through full exploitation of the nature of the W factors behavior in the FFT passes. The decomposition of the large FFT into smaller modules for this purpose is explored and a high throughput system (up to 2.2MHz for FFT's of up to 16K points) implementation based on this approach, with the Zoran ZR34161 Vector Signal Processor is presented.

A self-testing 2-/spl mu/m CMOS chip set for FFT applications

Abstract: A chip set for high-speed radix-2 fast Fourier transform (FFT) applications up to 512 points is described. The chip set comprises a (16+16)/spl times/(12+12)-bit complex number multiplier, and a 16-bit butterfly chip for data reordering, twiddle factor generation, and butterfly arithmetic. The chips have been implemented using a standard cell design methodology on a 2-/spl mu/m bulk CMOS process. Three chips implement a complex FFT butterfly with a throughput of 10 MHz, and are cascadable up to 512 points. The chips feature an offline self-testing capability.

Searching for the best Cooley-Tukey FFT algorithms

Abstract: The Cooley-Tukey input and output maps are used to developed the general topology of an FFT algorithm for a given length. Within this algorithm the twiddle factors can be placed in a nearly uncountable number of arrangements. From a given machine architecture one can choose a optimality criteria for the algorithm. With this optimality criteria the set of possible algorithms can be search for the best one. A exhaustive search is intractable for reasonable length algorithms. Thus, the search space has been hueristically reduced to make the problem tractable. An example of a length 32 minimum number of multiplies is included.

A Method for Validating Multidimensional Fast Fourier Transform (FFT) Algorithms

Abstract: : A method is described for validating fast Fourier transforms (FFTs) based on the use of simple input functions whose discrete Fourier transforms can be evaluated in closed form Explicit analytical results are developed for one dimensional and two dimensional discrete Fourier transforms The analytical results are easily generalized to higher dimensions The results offer a means for validating the FFT algorithm in one, two, or higher dimensional settings The general motivation for the work comes from the need to validate the FFT algorithm when it newly implemented on a computer or when new techniques or devices are added to a computer facility to evaluate discrete Fourier transforms Keywords: Computer Program Verification