The random failure statistics for the yield of mass-produced semiconductor integrated circuits are derived by considering defect and fault formation during the manufacturing process. This approach allows the development of a yield theory that includes many models that have been used previously and also results in a practical control model for integrated circuit manufacturing. Some simpler formulations of yield theory that have been described in the literature are compared to the model. Application of the model to yield management are discussed and examples given.

Integrated circuit yield statistics

In this paper we present a unified framework for prediction and estimation of the manufacturing yield of VLSI circuits. We formally introduce a number of yield measures that are useful both during the design process and during the manufacturing process. This framework is general enough to bridge the gap between the traditional concepts of parametric and catastrophic yield. We provide a classification of causes of yield loss which is essential for efficient yield estimation. Finally, we relate yield to manufacturing costs which provides a common denominator for the discussion of the manufacturing process efficiency.

VLSI Yield Prediction and Estimation: A Unified Framework

In a recent paper, see ibid., vol. Sc-9, no.3, p.86-95 (1974), Warner proposed a composite model to the monolithic IC yield problem. This composite model is a multiparameter fit to a set of data originally described by Moore (1970). It is shown that these same data can be modeled equally well with negative binomial statistics with two parameters.

On a composite model to the IC yield problem

While it is important to exhaustively verify IC designs for their functional performance, it is equally important to verify their robustness against spot defects, that is, to foresee what will happen to the design when it is exposed to defect conditions in a real manufacturing environment. One such verification is done by extracting the layout sites where defects can induce a functional failure of the design. Initial attempts to perform this verification task were based on a 'critical area extraction' of one layer at a time, neglecting the electrical significance of interrelationships between layers. A novel method to construct deterministically multilayer critical areas is presented. These critical areas are established on the theoretical basis of defect semantics and on the new concept of 'susceptible sites'. A system comprising several algorithms which in principle maintain simultaneously as many scan lines as the number of layers, in such a way that it is possible to keep track of the vertical and horizontal effects of defects, is developed. >

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IC defect sensitivity for footprint-type spot defects

Semiconductor manufacturing is a complex multistage manufacturing process, and wafer fabs use complex processes involving billions of dollars worth of equipment to produce integrated circuits. The level of complexities associated with an integrated circuit is increasing in terms of feature size and number of devices. Companies use several performance metrics such as defectiveness, yield, and cycle time to improve manufacturing performance. Maintaining high yield through reliable and accurate quality control measures is one of the key performance criteria used by companies. The intent of this paper is to provide a review of the literature dealing with critical aspects of yield modelling. A review of many topics from simple probabilistic yield models to the incorporation of critical features such as spatial defects and radial yield losses will be provided. We will also assess empirical techniques used to model variations associated with complex interrelated wafer manufacturing processes. We emphasize that y...

A review of yield modelling techniques for semiconductor manufacturing

Various attempts have been made to analyze the yield of integrated circuits in the presence of point defects. This paper analyzes the yield considering both radial and angular variation in the defect density. The effect of statistical variations in the average defect density from slice to slice is also included. Different types of defects which affect the yield are reviewed. The degradation in yield due to point defects, line defects, area defects, and defect clusters is considered in detail. A method of optimum chip placement is described, and the results of computer calculations showing yield as a function of chip size are given assuming different defect density distributions. The results are primarily applicable to large integrated circuit chips.

A. Gupta

Papers

Defect analysis and yield degradation of integrated circuits