A. Oishi

TL;DR: In this article, the most suitable STI filling process has been developed for 45nm-node SoC platform and the authors found that the stress induced anti-isotropic impurity diffusion caused the Vth lowering.

TL;DR: In this paper, the key device strategies for junction scaling, gate stack scaling, and stress-induced mobility enhancement are discussed for 45nm generation of CMOSFETs, and a systematic study on the process induced mobility enhancement is performed and it is confirmed that the new scheme such as eSiGe and stress liner techniques are suitable for the 45nm technology CMOS-FET.

TL;DR: In this paper, a solid-state image sensor has a semiconductor element substrate having a plurality of photo electric conversion elements, an interlaminar insulating film having wires, formed at a first surface of the semiconductor elements substrate, a color filter having a plethora of dye films and a shroud that surrounded each of the inner lenses.

TL;DR: In this article, a solid state imaging device includes a semiconductor substrate having an element isolating layer and a plurality of photoelectric conversion elements each formed in a respective one of a pixel regions.

TL;DR: In this article, the state-of-the-art 45nm high performance bulk logic platform technology was presented, which utilizes, for the first time in the industry, ultra high NA (1.07) immersion lithography to realize highly downscaled chip size.