Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

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High-κ gate dielectrics: Current status and materials properties considerations

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Field-effect transistors (FETs) based on semi-conductor nanowires could one day replace standard silicon MOSFETs in miniature electronic circuits. MOSFETs, or metal-oxide semiconductor field-effect transistors, are a type of transistor used for high-speed switching and in a computer's integrated circuits. A specially designed nanowire with a germanium shell and silicon core has shown promise as a nanometre-scale field-effect transistor: it has a near-perfect channel for electronic conduction. Now, in transistor configuration, this germanium/silicon nanowire is shown to have properties including high conductance and short switching time delay that are better than state-of-the-art silicon MOSFETs. In a transistor configuration, a new germanium/silicon nanowire has characteristics such as conductance, on-current and switching time delay that are better than those of state-of-the-art silicon metal-oxide-semiconductor field-effect transitors. Semiconducting carbon nanotubes1,2 and nanowires3 are potential alternatives to planar metal-oxide-semiconductor field-effect transistors (MOSFETs)4 owing, for example, to their unique electronic structure and reduced carrier scattering caused by one-dimensional quantum confinement effects1,5. Studies have demonstrated long carrier mean free paths at room temperature in both carbon nanotubes1,6 and Ge/Si core/shell nanowires7. In the case of carbon nanotube FETs, devices have been fabricated that work close to the ballistic limit8. Applications of high-performance carbon nanotube FETs have been hindered, however, by difficulties in producing uniform semiconducting nanotubes, a factor not limiting nanowires, which have been prepared with reproducible electronic properties in high yield as required for large-scale integrated systems3,9,10. Yet whether nanowire field-effect transistors (NWFETs) can indeed outperform their planar counterparts is still unclear4. Here we report studies on Ge/Si core/shell nanowire heterostructures configured as FETs using high-κ dielectrics in a top-gate geometry. The clean one-dimensional hole-gas in the Ge/Si nanowire heterostructures7 and enhanced gate coupling with high-κ dielectrics give high-performance FETs values of the scaled transconductance (3.3 mS µm-1) and on-current (2.1 mA µm-1) that are three to four times greater than state-of-the-art MOSFETs and are the highest obtained on NWFETs. Furthermore, comparison of the intrinsic switching delay, τ = CV/I, which represents a key metric for device applications4,11, shows that the performance of Ge/Si NWFETs is comparable to similar length carbon nanotube FETs and substantially exceeds the length-dependent scaling of planar silicon MOSFETs.

Ge/Si nanowire heterostructures as high-performance field-effect transistors

Hafnium and zirconium silicate (HfSixOy and ZrSixOy, respectively) gate dielectric films with metal contents ranging from ∼3 to 30 at. % Hf, or 2 to 27 at. % Zr (±1 at. % for Hf and Zr, respectively, within a given film), have been investigated, and films with ∼2–8 at. % Hf or Zr exhibit excellent electrical properties and high thermal stability in direct contact with Si. Capacitance–voltage measurements show an equivalent oxide thickness tox of about 18 A (21 A) for a 50 A HfSixOy (50 A ZrSixOy) film deposited directly on a Si substrate. Current–voltage measurements show for the same films a leakage current of less than 2×10−6 A/cm2 at 1.0 V bias. Hysteresis in these films is measured to be less than 10 mV, the breakdown field is measured to be EBD∼10 MV/cm, and the midgap interface state density is estimated to be Dit∼1–5×1011 cm−2 eV−1. Au electrodes produce excellent electrical properties, while Al electrodes produce very good electrical results, but also react with the silicates, creating a lower e l...

Hafnium and zirconium silicates for advanced gate dielectrics

Starting with a brief review on 0.1-/spl mu/m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may lead to the outermost limits of silicon scaling.

CMOS scaling into the nanometer regime

In this paper, normal operation of a MOSFET with an ultra-thin direct-tunneling gate oxide is reported for the first time. These high current drive n-MOSFET's were fabricated with a 1.5 nm direct-tunneling gate oxide. They operate well at gate lengths of around 0.1 /spl mu/m, because the gate leakage current falls in proportional to the gate length, while the drain current increases in inverse proportion. A current drive of more than 1.0 mA//spl mu/m and a transconductance of more than 1,000 mS/mm were obtained at a gate length of 0.09 /spl mu/m at room temperature. These are the highest values ever obtained with Si MOSFET's at room temperature. Further, hot-carrier reliability is shown to improve as the thickness of the gate oxide is reduced, even in the 1.5 nm case. This work clarifies that excellent performance-a transconductance of over 1,000 mS/mm at room temperature-can be obtained with Si MOSFET's if a high-capacitance gate insulator is used.

1.5 nm direct-tunneling gate oxide Si MOSFET's

The sheet resistance of TiSi/sub 2/-polycide (TiSi/sub 2/-polysilicon) lines increases as they are made narrower. This phenomenon has been investigated in detail. It is found that the relationship between sheet resistance and line width (W) is characterized by three distinct regions according to the value of W. The abrupt increase in sheet resistance observed in the region W/spl les/0.2 /spl mu/m cannot be explained in terms of the phase transition from C54 to C49, which we show to be the cause of the rising resistance at larger W. By adopting a new test pattern for sheet resistance measurements and using it in combination with TEM and EDX analysis we conclude that the cause of this abrupt increase is the presence of large inter-grain layers where silicide is very sparse. On the contrary, NiSi films have no such inter-grain layers, and good resistance values can be obtained even with 0.1 /spl mu/m lines. The NiSi process appears to be a suitable candidate to replace TiSi/sub 2/ in future deep-sub-micron high-speed CMOS devices. >

Analysis of resistance behavior in Ti- and Ni-salicided polysilicon films

Forty-nanometer gate length n-MOSFETs with ultra-shallow source and drain junctions of around 10 nm are fabricated for the first time To achieve such shallow junctions, a technique of solid-phase diffusion (SPD) from phosphorous-doped silicated glass (PSG) gate sidewalls is used The resulting 40 nm gate length n-MOSFETs operate quite normally at room temperature Even in the sub-50 nm region, short-channel effects-V/sub th/ shift and S-factor degradation-are suppressed very well The impact ionization rate falls significantly as Vd falls below 15 V It is found that, in the case of Vd less than 15 V, hot-carrier degradation is not a serious problem even in the sub-50 nm region >

Sub-50 nm gate length n-MOSFETs with 10 nm phosphorus source and drain junctions

This work is a systematic investigation of the feasibility of MOSFET's with a gate length below 0.1 /spl mu/m. Limits imposed on the scalability of oxide thickness and supply voltage require a new scaling methodology which allows these parameters to be maintained constant. The feasibility of achieving sub-0.1 /spl mu/m MOSFETs in this way is evaluated through simulations of the electrical characteristics of several different device structures and by addressing the most important issues related to the scaling down to ultra-short gate lengths. This study forms a valuable starting point for the understanding of technological requirements for future ULSI. >

Scaling the MOS transistor below 0.1 /spl mu/m: methodology, device structures, and technology requirements

Forty nm gate length n-MOSFETs with ultra-shallow source and drain junctions of around 10 nm are fabricated for the first time. In order to fabricate such small geometry MOSFETs, two special techniques have been adopted. One is a resist thinning technique using isotropic oxygen plasma ashing for the fabrication of 40 nm gate electrodes. The other is a solid phase diffusion technique from phosphorus doped silicated glass (PSG) for the fabrication of 10 nm source and drain junctions. The resulting 40 mm gate length n-MOSFETs operate quite normally at room temperature. Using these n-MOSFETs, we investigated short channel effects and current drivability in the 40 nm region at room temperature. We have also investigated hot-carrier related phenomena in the 40-nm region. Results indicate that the impact ionization rate increases slightly as the gate length is reduced to around 40 nm, and that both impact ionization rate and substrate current fall significantly as V/sub d/ falls below 1.5 V. This demonstrates that reliability as regards degradation due to hot carriers is not a serious problem even in the 40 mm region if V/sub d/ is less than or equal to 1.5 V. >

Masanobu Saito

Papers

1.5 nm direct-tunneling gate oxide Si MOSFET's

Analysis of resistance behavior in Ti- and Ni-salicided polysilicon films

Sub-50 nm gate length n-MOSFETs with 10 nm phosphorus source and drain junctions

Scaling the MOS transistor below 0.1 /spl mu/m: methodology, device structures, and technology requirements

A 40 nm gate length n-MOSFET