The use of VCO-based quantization within continuous-time (CT) SigmaDelta analog-to-digital converter (ADC) structures is explored, with a custom prototype in 0.13 mum CMOS showing measured performance of 86/72 dB SNR/SNDR with 10 MHz bandwidth while consuming 40 mW from a 1.2 V supply and occupying an active area of 640 mum times 660 mum. A key element of the ADC structure is a 5-bit VCO-based quantizer clocked at 950 MHz which achieves first-order noise shaping of its quantization noise. The quantizer structure allows the second-order CT SigmaDelta ADC topology to achieve third-order noise shaping, and direct connection of the VCO-based quantizer to the internal DACs of the ADC provides intrinsic dynamic element matching of the DAC elements.

/pdf/a-12-bit-10-mhz-bandwidth-continuous-time-sigma-delta-adc-4lgzviw47n.pdf

A 12-Bit, 10-MHz Bandwidth, Continuous-Time $\Sigma\Delta$ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer

The use of VCO-based quantization within continuous-time (CT) ΣΔ analog-to-digital converter (ADC) structures is explored, with a custom prototype in 0.13 μm CMOS showing measured performance of 86/72 dB SNR/SNDR with 10 MHz bandwidth while consuming 40 mW from a 1.2 V supply and occupying an active area of 640 μm × 660 μm. A key element of the ADC structure is a 5-bit VCO-based quantizer clocked at 950 MHz which achieves first-order noise shaping of its quantization noise. The quantizer structure allows the second-order CT SA ADC topology to achieve third-order noise shaping, and direct connection of the VCO-based quantizer to the internal DACs of the ADC provides intrinsic dynamic element matching of the DAC elements.

A 12-Bit, 10-MHz Bandwidth, Continuous-Time ΣΔ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer

A voltage-controlled oscillator (VCO) based analog-to-digital converter (ADC) is a time-based architecture with a first-order noise-shaping property, which can be implemented using a VCO and digital circuits. This paper analyzes the performance of VCO-based ADCs in the presence of nonidealities such as jitter, nonlinearity, mismatch, and the metastability of D flip-flops. Based on this analysis, design criteria for determining parameters for VCO-based ADCs are described. In addition, a digital calibration technique to enhance the spurious-free dynamic range degraded by the nonlinearity is also introduced. To verify the theoretical analysis, a prototype chip is implemented in a 0.13-?m CMOS process. With a 500-MHz sampling frequency, the prototype achieves a signal-to-noise ratio ranging from 71.8 to 21.3 dB for an input bandwidth of 100 kHz-247 MHz, while dissipating 12.6 mW and occupying an area of 0.078 mm2.

Analysis and Design of Voltage-Controlled Oscillator Based Analog-to-Digital Converter

We present an area-efficient neural signal-acquisition system that uses a digitally intensive architecture to reduce system area and enable operation from a 0.5 V supply. The architecture replaces ac coupling capacitors and analog filters with a dual mixed-signal servo loop, which allows simultaneous digitization of the action and local field potentials. A noise-efficient DAC topology and an compact, boxcar sampling ADC are used to cancel input offset and prevent noise folding while enabling “per-pixel” digitization, alleviating system-level complexity. Implemented in a 65 nm CMOS process, the prototype occupies 0.013 mm2 while consuming 5 μW and achieving 4.9 μVrms of input-referred noise in a 10 kHz bandwidth.

A 0.013 ${\hbox {mm}}^{2}$ , 5 $\mu\hbox{W}$ , DC-Coupled Neural Signal Acquisition IC With 0.5 V Supply

Analysis and design of voltage-controlled oscillator based analog-to-digital converter = 전압조절발진기 기반 아날로그 디지털 변환기의 해석과 설계

This paper describes a new first- and second-order delta-sigma modulator concept where the first integrator is extracted and implemented by a frequency modulator with the modulating signal as the input. The result is a simple delta-sigma modulator with no need for digital-to-analog converters, allowing straightforward multibit quantization. Without the frequency modulator, the circuit becomes a frequency-to-digital converter with delta-sigma noise shaping. An experimental first- and second-order modulator has been implemented in a 1.2-/spl mu/m standard digital CMOS process and the results confirm the theory. For the first-order modulator an input signal amplitude of 150 mV resulted in a signal-to-quantization noise ratio (SQNR) of /spl ap/115 dB at 2 MHz sampling frequency and signal bandwidth of 500 Hz.

Delta-sigma modulators using frequency-modulated intermediate values

A novel second-order cascaded Delta - Sigma modulator concept is presented. The first integrator is extracted, and implemented by an FM oscillator. The result is a simple, extended multibit Delta - Sigma modulator with no component matching restrictions, and a high sampling frequency potential. Without the oscillator, the modulator becomes a second-order Delta - Sigma F/D converter.

Novel second-order Δ-Σ modulator/frequency-to-digital converter

This paper describes a new first and second-order delta-sigma modulator (DSM) concept where the first integrator is extracted and implemented by a FM oscillator with the modulating signal as the input. The result is a simple DSM with no need for DACs, allowing straightforward multi-bit quantization. Without the FM oscillator, the modulator becomes a F/D converter with delta-sigma noise shaping.

A. Olsen

Papers

Delta-sigma modulators using frequency-modulated intermediate values

Novel second-order Δ-Σ modulator/frequency-to-digital converter

Delta-sigma converters using frequency-modulated intermediate values