Showing papers in "IEEE Journal of Solid-state Circuits in 1997"

A 1.5-V, 1.5-GHz CMOS low noise amplifier

Abstract: A 1.5-GHz low noise amplifier (LNA), intended for use in a global positioning system (GPS) receiver, has been implemented in a standard 0.6-/spl mu/m CMOS process. The amplifier provides a forward gain (S21) of 22 dB with a noise figure of only 3.5 dB while drawing 30 mW from a 1.5 V supply. In this paper, we present a detailed analysis of the LNA architecture, including a discussion on the effects of induced gate noise in MOS devices.

Low-power logic styles: CMOS versus pass-transistor logic

Abstract: Recently reported logic style comparisons based on full-adder circuits claimed complementary pass-transistor logic (CPL) to be much more power-efficient than complementary CMOS. However, new comparisons performed on more efficient CMOS circuit realizations and a wider range of different logic cells, as well as the use of realistic circuit arrangements demonstrate CMOS to be superior to CPL in most cases with respect to speed, area, power dissipation, and power-delay products. An implemented 32-b adder using complementary CMOS has a power-delay product of less than half that of the CPL version. Robustness with respect to voltage scaling and transistor sizing, as well as generality and ease-of-use, are additional advantages of CMOS logic gates, especially when cell-based design and logic synthesis are targeted. This paper shows that complementary CMOS is the logic style of choice for the implementation of arbitrary combinational circuits if low voltage, low power, and small power-delay products are of concern.

Supply and threshold voltage scaling for low power CMOS

Abstract: This paper investigates the effect of lowering the supply and threshold voltages on the energy efficiency of CMOS circuits. Using a first-order model of the energy and delay of a CMOS circuit, we show that lowering the supply and threshold voltage is generally advantageous, especially when the transistors are velocity saturated and the nodes have a high activity factor, In fact, for modern submicron technologies, this simple analysis suggests optimal energy efficiency at supply voltages under 0.5 V. Other process and circuit parameters have almost no effect on this optimal operating point. If there is some uncertainty in the value of the threshold or supply voltage, however, the power advantage of this very low voltage operation diminishes. Therefore, unless active feedback is used to control the uncertainty, in the future the supply and threshold voltage will not decrease drastically, but rather will continue to scale down to maintain constant electric fields.

A 1.8-GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors

Abstract: A completely integrated 1.8-GHz low-phase-noise voltage-controlled oscillator (VCO) has been realized in a standard silicon digital CMOS process. The design relies heavily on the integrated spiral inductors which have been realized with only two metal layers and without etching. The effects of high-frequency magnetic fields and losses in the heavily doped substrate have been simulated and modeled with finite-element analysis. The achieved phase noise is as low as -116 dBc/Hz at an offset frequency of 600 kHz, at a power consumption of only 6 mW. The VCO is tuned with standard available junction capacitances, resulting in a 250-MHz tuning range.

The modeling, characterization, and design of monolithic inductors for silicon RF IC's

Abstract: The results of a comprehensive investigation into the characteristics and optimization of inductors fabricated with the top-level metal of a submicron silicon VLSI process are presented. A computer program which extracts a physics-based model of microstrip components that is suitable for circuit (SPICE) simulation has been used to evaluate the effect of variations in metallization, layout geometry, and substrate parameters upon monolithic inductor performance. Three-dimensional (3-D) numerical simulations and experimental measurements of inductors were also used to benchmark the model accuracy. It is shown in this work that low inductor Q is primarily due to the restrictions imposed by the thin interconnect metallization available in most very large scale integration (VLSI) technologies, and that computer optimization of the inductor layout can be used to achieve a 50% improvement in component Q-factor over unoptimized designs.

CMOS active pixel image sensors for highly integrated imaging systems

Abstract: A family of CMOS-based active pixel image sensors (APSs) that are inherently compatible with the integration of on-chip signal processing circuitry is reported. The image sensors were fabricated using commercially available 2-/spl mu/m CMOS processes and both p-well and n-well implementations were explored. The arrays feature random access, 5-V operation and transistor-transistor logic (TTL) compatible control signals. Methods of on-chip suppression of fixed pattern noise to less than 0.1% saturation are demonstrated. The baseline design achieved a pixel size of 40 /spl mu/m/spl times/40 /spl mu/m with 26% fill-factor. Array sizes of 28/spl times/28 elements and 128/spl times/128 elements have been fabricated and characterized. Typical output conversion gain is 3.7 /spl mu/V/e/sup -/ for the p-well devices and 6.5 /spl mu/V/e/sup -/ for the n-well devices. Input referred read noise of 28 e/sup -/ rms corresponding to a dynamic range of 76 dB was achieved. Characterization of various photogate pixel designs and a photodiode design is reported. Photoresponse variations for different pixel designs are discussed.

A 1.9-GHz wide-band IF double conversion CMOS receiver for cordless telephone applications

Abstract: A monolithic 1.9-GHz, 198-mW, 0.6-/spl mu/m CMOS receiver which meets the specifications of the Digital Enhanced Cordless Telecommunications (DECT) standard is described. All of the RF, IF, and baseband receiver components, with the exception of the frequency synthesizers, have been integrated into a single chip solution. A description is given of a wide-band IF with double conversion architecture which eliminates the need for the discrete-component noise and IF filters in addition to facilitating the eventual integration of the frequency synthesizer blocks with on-chip VCO's. The prototype device utilizes a 3.3-V supply and includes a low noise amplifier, an image-rejection mixer, and two quadrature baseband signal paths each of which includes a second-order Sallen and Key anti-alias filter, an eighth-order switched-capacitor filter network followed by a 10-b pipelined analog-to-digital converter (ADC). The experimental device has a measured receiver reference sensitivity of -90 dBm, an input referred IP3 of -7 dBm, a P/sub -1 dB/ of -24 dBm, and an image-rejection ratio of -55 dBc across the DECT bands.

A semidigital dual delay-locked loop

Abstract: This paper describes a dual delay-locked loop architecture which achieves low jitter, unlimited (modulo 2/spl pi/) phase shift, and large operating range. The architecture employs a core loop to generate coarsely spaced clocks, which are then used by a peripheral loop to generate the main system clock through phase interpolation. The design of an experimental prototype in a 0.8-/spl mu/m CMOS technology is described. The prototype achieves an operating range of 80 kHz-400 MHz. At 250 MHz, its peak-to-peak jitter with quiescent supply is 68 ps, and its jitter supply sensitivity is 0.4 ps/mV.

A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation

Abstract: A digital compensation method and key circuits are presented that allow fractional-N synthesizers to be modulated at data rates greatly exceeding their bandwidth. Using this technique, a 1.8-GHz transmitter capable of digital frequency modulation at 2.5 Mb/s can be achieved with only two components: a frequency synthesizer and a digital transmit filter. A prototype transmitter was constructed to provide proof of concept of the method; its primary component is a custom fractional-N synthesizer fabricated in a 0.6-/spl mu/m CMOS process that consumes 27 mW. Key circuits on the custom IC are an on-chip loop filter that requires no tuning or external components, a digital MASH /spl Sigma/-/spl Delta/ modulator that achieves low power operation through pipelining, and an asynchronous, 64-modulus divider (prescaler). Measurements from the prototype indicate that it meets performance requirements of the digital enhanced cordless telecommunications (DECT) standard.

A dynamic analysis of the Dickson charge pump circuit

Abstract: Dynamics of the Dickson charge pump circuit are analyzed. The analytical results enable the estimation of the rise time of the output voltage and that of the power consumption during boosting. By using this analysis, the optimum number of stages to minimize the rise time has been estimated as 1.4 N/sub min/, where N/sub min/ is the minimum value of the number of stages necessary for a given parameter set of supply voltage, threshold voltage of transfer diodes, and boosted voltage. Moreover, the self-load capacitance of the charge pump, which should be charged up at the same time as the output load capacitance of the charge pump, has been estimated as about one-third of the total charge pump capacitance. As a result, the equivalent circuit of the charge pump has been modified. The analytical results are in good agreement with simulation by the iteration method, typically within 10% for the rise time and within 2% for the power consumption. In the case of a charge pump with MOS transfer transistors, the analytical results of the rise time agree with the SPICE simulation within 10%.

A scalable high-frequency noise model for bipolar transistors with application to optimal transistor sizing for low-noise amplifier design

Abstract: Fully scalable, analytical HF noise parameter equations for bipolar transistors are presented and experimentally tested on high-speed Si and SiGe technologies. A technique for extracting the complete set of transistor noise parameters from Y parameter measurements only is developed and verified. Finally, the noise equations are coupled with scalable variants of the HICUM and SPICE-Gummel-Poon models and are employed in the design of tuned low noise amplifiers (LNA's) in the 1.9-, 2.4-,and 5.8-GHz bands.

Jitter in ring oscillators

Abstract: Jitter in ring oscillators is theoretically described, and predictions are experimentally verified. A design procedure is developed in the context of time domain measures of oscillator jitter in a phase-locked loop (PLL). A major contribution is the identification of a design figure of merit /spl kappa/, which is independent of the number of stages in the ring. This figure of merit is used to relate fundamental circuit-level noise sources (such as thermal and shot noise) to system-level jitter performance. The procedure is applied to a ring oscillator composed of bipolar differential pair delay stages. The theoretical predictions are tested on 155 and 622 MHz clock-recovery PLL's which have been fabricated in a dielectrically isolated, complementary bipolar process. The measured closed-loop jitter is within 10% of the design procedure prediction.

CMOS current reference without resistance

Abstract: A micropower current reference in the range of 1 to 100 nA is built with CMOS transistors only, featuring low sensitivity with respect to technology and temperature. Supply voltage can be as low as 1.2 V. This autonomous circuit is simple and occupies a surface area of 0.06 mm/sup 2/.

The MICROMIXER: a highly linear variant of the Gilbert mixer using a bisymmetric Class-AB input stage

Abstract: This paper outlines the basic theory of a development of the Gilbert mixer. The bipolar junction transistor (BJT) differential pair widely used as the RF input stage is replaced by a bisymmetric Class-AB topology based on translinear principles. It does not have inherent gain compression, affording a greatly extended signal capacity. The linearity of variants of the basic form is excellent, providing two-tone intermodulation intercepts as high as +30 dBm, without the expenditure of high bias currents. It can operate on supplies as low as 2.2 V, with a power consumption of under 5 mW. The input impedance of this mixer is accurately controllable (typically 50 /spl Omega/) and provides a true broadband match. The noise figure depends on design details and is generally not as low as in mixers specifically optimized for noise performance, although acceptable for many receiver applications. Inductively degenerated variants can be tuned to a narrowband match at microwave frequencies and provide full-mixing SSB noise figures as low as 6.5 dB, Practical realizations are in use in applications to 1.9 GHz.

A 1-V high-speed MTCMOS circuit scheme for power-down application circuits

Abstract: This paper proposes a new multithreshold-voltage CMOS circuit (MTCMOS) concept aimed at achieving high-speed, ultralow-power large-scale integrators (LSI's) for battery-driven portable equipment. The "balloon" circuit scheme based on this concept preserves data during the power-down period in which the power supply to the circuit is cut off in order to reduce the standby power. Low-power, high-speed performance is achieved by the small preserving circuit which can be separated from the critical path of the logic circuit. This preserving circuit is not only three times faster than a conventional MTCMOS one, but it consumes half the power and takes up half the area. Using this scheme for an LSI chip, 20-MHz operation at 1.0 V and only a few nA standby current was achieved with 0.5-/spl mu/m CMOS technology. Moreover, this scheme is effective for high speed and low-power operation in quarter-micrometer and finer devices.

New single-clock CMOS latches and flipflops with improved speed and power savings

Abstract: New dynamic, semistatic, and fully static single-clock CMOS latches and flipflops are proposed. By removing the speed and power bottlenecks of the original true-single-phase clocking (TSPC) and the existing differential latches and flipflops, both delays and power consumptions are considerably reduced. For the nondifferential dynamic, the differential dynamic, the semistatic, and the fully static flipflops, the best reduction factors are 1.3, 2.1, 2.2, and 2.4 for delays and 1.9, 3.5, 3.4, and 6.5 for power-delay products with an average activity ratio (0.25), respectively. The total and the clocked transistor numbers are decreased. In the new differential flipflops, clock loads are minimized and logic-related transistors are purely n-type in both n- and p-latches, giving additional speed advantage to this kind of CMOS circuits.

A 1.8-V digital-audio sigma-delta modulator in 0.8-/spl mu/m CMOS

Abstract: Oversampling techniques based on sigma-delta (/spl Sigma//spl Delta/) modulation offer numerous advantages for the realization of high-resolution analog-to-digital (A/D) converters in low-voltage environment. This paper examines the design and implementation of a CMOS /spl Sigma//spl Delta/ modulator for digital-audio A/D conversion that operates from a single 1.8-V power supply. A cascaded modulator that maintains a large full-scale input range while avoiding signal clipping at internal nodes is introduced. The experimental modulator has been designed with fully differential switched-capacitor integrators employing different input and output common-mode levels and boosted clock drivers in order to facilitate low voltage operation. Precise control of common-mode levels, high power supply noise rejection, and low power dissipation are obtained through the use of two-stage, class A/AB operational amplifiers. At a sampling rate of 4 MHz and an oversampling ratio of 80, an implementation of the modulator in a 0.8-/spl mu/m CMOS technology with metal-to-polycide capacitors and NMOS and PMOS threshold voltages of +0.65 V and -0.75 V, respectively, achieves a dynamic range of 99 dB at a Nyquist conversion rate of 50 kHz. The modulator can operate from supply voltages ranging from 1.5-2.5 V, occupies an active area of 1.5 mm/sup 2/, and dissipates 2.5 mW from a 1.8-V supply.

A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers

Abstract: A parallel-pipelined A/D converter with an area and power efficient architecture is described. By sharing amplifiers along the pipeline and also completely eliminating the amplifier from the last stage, an 8-b pipeline is realized using just three amplifiers (instead of seven amplifiers with a conventional pipeline architecture). By using two such pipelines in parallel, a 52 Msamples/s prototype A/D converter that is Intended for a switched digital video application has been implemented in a 0.9-/spl mu/m CMOS technology. The device occupies 15 mm/sup 2/ and dissipates 250 mW from a 5 V supply.

Multistage amplifier topologies with nested G/sub m/-C compensation

Abstract: This paper presents a multistage amplifier for low-voltage applications (<2 V). The amplifier consists of simple (noncascode) low gain stages and is stabilized using a nested transconductance-capacitance compensation (NGCC) scheme. The resulting topology is similar to the well known nested Miller compensation (NMC) multistage amplifier, except that the proposed topology contains extra G/sub m/ feedforward stages which are used to enhance the amplifier performance. The NGCC simplifies the transfer function of the proposed multistage amplifier which, in turn, simplifies its stability conditions. A comparison between the NGCC and NMC shows that the NGCC has wider bandwidth and is easier to stabilize. A four-stage NGCC amplifier has been fabricated using a 2-/spl mu/m CMOS process and is tested using a /spl plusmn/1.0 V power supply. A dc gain of 100 dB has been measured. A gain bandwidth product of 1 MHz with 58/spl deg/ of phase margin and power of 1.4 mW can be achieved. The op amp occupies an active area of 0.22 mm/sup 2/. Step response shows that the op amp is stable.

An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm/sup 2/

Abstract: A distributed-gain preamplifier uses averaging to improve resolution by 4 b in differential nonlinearity (DNL) and 2 b in integral nonlinearity (INL) in a flash analog-to-digital converter (ADC). Fabricated in a 0.5-/spl mu/m, triple-metal, single-poly CMOS process, the circuit measures 1.4 mm/spl times/1.4 mm including a bandgap and a sample-and-hold (SH), while the ADC itself occupies 1-mm/sup 2/. At a conversion rate of 50-MS/s the ADC dissipates 170 mW, the SH dissipates 70 mW, and the untrimmed ADC-plus-SH exhibits 54 dB S/(N+D) with a 12-MHz 90% full-scale input.

A cascaded sigma-delta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR

Abstract: A low-noise multibit sigma-delta analog-to-digital converter (ADC) architecture suitable for operation at low oversampling ratios is presented. The ADC architecture uses an efficient high-resolution pipelined quantizer while avoiding loop stability degradation caused by pipeline latency. A 16-b implementation of the architecture, fabricated in a 0.6-/spl mu/m CMOS process, cascades a second-order 5-b sigma-delta modulator with a four-stage 12-b pipelined ADC and operates at a low 8X oversampling ratio. Static and dynamic linearity of the integrated ADC are improved through the use of dynamic element matching techniques and the use of bootstrapped and clock-boosted input switches. The ADC operates at a 20 MHz clock rate and dissipates 550 mW with a 5 V/3 V analog/digital supply. It achieves an SNR of 89 dB over a 1.25-MHz signal bandwidth and a total harmonic distortion (THD) of -98 dB with a 100-kHz input signal.

Delta-sigma modulators using frequency-modulated intermediate values

Abstract: This paper describes a new first- and second-order delta-sigma modulator concept where the first integrator is extracted and implemented by a frequency modulator with the modulating signal as the input. The result is a simple delta-sigma modulator with no need for digital-to-analog converters, allowing straightforward multibit quantization. Without the frequency modulator, the circuit becomes a frequency-to-digital converter with delta-sigma noise shaping. An experimental first- and second-order modulator has been implemented in a 1.2-/spl mu/m standard digital CMOS process and the results confirm the theory. For the first-order modulator an input signal amplitude of 150 mV resulted in a signal-to-quantization noise ratio (SQNR) of /spl ap/115 dB at 2 MHz sampling frequency and signal bandwidth of 500 Hz.

Quadrature bandpass /spl Delta//spl Sigma/ modulation for digital radio

Abstract: A quadrature bandpass /spl Delta//spl Sigma/ modulator IC facilitates monolithic digital-radio-receiver design by allowing straightforward "complex A/D conversion" of an image reject mixer's I and Q, outputs Quadrature bandpass /spl Delta//spl Sigma/ modulators provide superior performance over pairs of real bandpass /spl Delta//spl Sigma/ modulators in the conversion of complex input signals, using complex filtering embedded in /spl Delta//spl Sigma/ loops to efficiently realize asymmetric noise-shaped spectra The fourth-order prototype IC, clocked at 10 MHz, converts narrowband 375-MHz I and Q inputs and attains a dynamic range of 67 dB in 200-kHz (GSM) bandwidth, increasing to 71 and 77 dB in 100- and 30-kHz bandwidths, respectively Maximum signal-to-noise plus distortion ratio (SNDR) in 200-kHz bandwidth is 62 dB Power consumption is 130 mW at 5 V Die size in a 08-/spl mu/m CMOS process is 24/spl times/18 mm/sup 2/

Efficiency improvement in charge pump circuits

Abstract: Conventional charge pump circuits use a fixed switching frequency that leads to power efficiency degradation for loading less than the rated loading. This paper proposes a level shifter design that also functions as a frequency converter to automatically vary the switching frequency of a dual charge pump circuit according to the loading. The switching frequency is designed to be 25 kHz with 12 mA loading on both inverting and noninverting outputs. The switching frequency is automatically reduced when loading is lighter to improve the power efficiency. The frequency tuning range of this circuit is designed to be from 100 Hz to 25 kHz. A start-up circuit is included to ensure proper pumping action and avoid latch-up during power-up. A slow turn-on, fast turn-off driving scheme is used in the clock buffer to reduce power dissipation. The new dual charge pump circuit was fabricated in a 3-/spl mu/m p-well double-poly single-metal CMOS technology with breakdown voltage of 18 V, the die size is 4.7/spl times/4.5 mm/sup 2/. For comparison, a charge pump circuit with conventional level shifter and clock buffer was also fabricated. The measured results show that the new charge pump has two advantages: (1) the power dissipation of the charge pump is improved by a factor of 32 at no load and by 2% at rated loading of 500 /spl Omega/ and (2) the breakdown voltage requirement is reduced from 19.2 to 17 V.

Low voltage performance of a microwave CMOS Gilbert cell mixer

Abstract: This paper demonstrates the low voltage operation of a doubly balanced Gilbert mixer fabricated in a 0.8-/spl mu/m CMOS process and operating as both a down-converter and an up-converter. As a down-converter with an RF input of 1.9 GHz, the mixer has a single sideband noise figure as low as 7.8 dB and achieved down-conversion gain for supply voltages as low as 1.8 V. As an up-converter, the mixer demonstrates 10 dB of conversion gain at an RF frequency of 2.4 GHz with an applied local oscillator (LO) power of -7 dBm and LO-RF/LO-IF isolation of at least 30 dB. Up-conversion gain was achieved over a 5-GHz bandwidth and at supply voltages as low as 1.5 V. The mixer presented demonstrates the lowest single side band noise figure for a CMOS doubly balanced down-converting mixer and the highest frequency of operation for a mixer fabricated in CMOS technology to date.

A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme

Abstract: A high-speed ring oscillator is proposed for improved operation frequency over those based on the conventional n-stage inverter chain. The ring oscillator consists of inverters with negative delay elements that are derived from the ring oscillator circuit. The cell delay of the ring oscillator is smaller than a fundamental inverter delay. Simulations show that the resulting operating frequencies are 50% higher than those obtainable from the conventional approaches.

Monolithic magnetic Hall sensor using dynamic quadrature offset cancellation

Abstract: The offset voltage and its temperature drift and production spread, which generally degrades the zero-level stability and reproducibility of magnetic Hall sensors, can be reduced using a single Hall plate and switching means for periodic permutation of the supply and output contact pairs. The present work describes a chopper-based 5-V monolithic linear Hall sensor with a /spl plusmn/0.1 T full scale where this dynamic plate offset cancellation technique has been employed together with a cost-effective signal conditioner. The device was integrated using a 2-/spl mu/m conventional BiCMOS process and the final chip, measuring 15/spl times/1.5 mm/sup 2/, shows, after packaging in a 3-pin plastic package, a residual offset with a production spread and a temperature-induced drift five to ten times smaller than in currently used multiplate dc quadrature cancellation approaches. The device does not require external components and provides an output free of HF residues.

A history of the invention of the transistor and where it will lead us

Abstract: Fifty years ago, in November 1947, John Bardeen and Walter Brattain discovered the transistor on the fourth floor of Building 1 at Bell Labs in Murray Hill, NJ. Fifty years later, the authors are still working with silicon but it is a very different silicon effort. Currently with the silicon optical bench they are trying to integrate optical components the way transistors have been over the last 50 years. So, silicon technology is still progressing. When considering the invention of the transistor, the authors note that the work of Bardeen and Brattain was really a discovery not an invention. At the time they discovered transistor action, they were investigating the nature of surface states and ways to reduce their presence. It was only later that things really became clear as to what was going on. Fifty years later that discovery is celebrated, and the authors present a brief history of the major events and the key people involved.

A 0.8-/spl mu/m CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage

Abstract: This paper presents a CMOS chip for the parallel acquisition and concurrent analog processing of two-dimensional (2-D) binary images. Its processing function is determined by a reduced set of 19 analog coefficients whose values are programmable with 7-b accuracy. The internal programming signals are analog, but the external control interface is fully digital. On-chip nonlinear digital-to-analog converters (DAC's) map digitally coded weight values into analog control signals, using feedback to predistort their transfer characteristics in accordance to the response of the analog programming circuitry. This strategy cancels out the nonlinear dependence of the analog circuitry with the programming signal and reduces the influence of interchip technological parameters random fluctuations. The chip includes a small digital RAM memory to store eight sets of processing parameters in the periphery of the cell array and four 2-D binary images spatially distributed over the processing array. It also includes the necessary control circuitry to realize the stored instructions in any order and also to realize programmable logic operations among images. The chip architecture is based on the cellular neural/nonlinear network universal machine (CNN-UM). It has been fabricated in a 0.8-/spl mu/m single-poly double-metal technology and features 2-/spl mu/s operation speed (time required to process an image) and around 7-b accuracy in the analog processing operations.

A 1-Gb/s, four-state, sliding block Viterbi decoder

Abstract: To achieve unlimited concurrency and hence throughput in an area-efficient manner, a sliding block Viterbi decoder (SBVD) is implemented that combines the filtering characteristics of a sliding block decoder with the computational efficiency of the Viterbi algorithm. The SBVD approach reduces decode of a continuous input stream to decode of independent overlapping blocks, without constraining the encoding process. A systolic SBVD architecture is presented that combines forward and backward processing of the block interval. The architecture is demonstrated in a four-state, R=1/2, eight-level soft decision Viterbi decoder that has been designed and fabricated in double-metal CMOS. The 9.21 mm/spl times/8.77 mm chip containing 150 k transistors is fully functional at a clock rate of 83 MHz and dissipates 3.0 W under typical operating conditions (V/sub DD/=5.0 V, T/sub A/=27/spl deg/C). This corresponds to a block decode rate of 83 MHz, equivalent to a decode rate of 1 Gb/s. For low-power operation, typical parts are fully functional at a clock rate of greater than 12 MHz, equivalent to a decode rate of 144 Mb/s, and dissipate 24 mW at V/sub DD/=1.5 V, demonstrating extremely low power consumption at such high rates.