Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

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Fundamentals of Modern VLSI Devices

Wafer bonding with intermediate polymer adhesives is an important fabrication technique for advanced microelectronic and microelectromechanical systems, such as three-dimensional integrated circuits, advanced packaging, and microfluidics. In adhesive wafer bonding, the polymer adhesive bears the forces involved to hold the surfaces together. The main advantages of adhesive wafer bonding include the insensitivity to surface topography, the low bonding temperatures, the compatibility with standard integrated circuit wafer processing, and the ability to join different types of wafers. Compared to alternative wafer bonding techniques, adhesive wafer bonding is simple, robust, and low cost. This article reviews the state-of-the-art polymer adhesive wafer bonding technologies, materials, and applications.

Adhesive wafer bonding

This review of design principles for implementation of a spiral inductor in a silicon integrated circuit fabrication process summarizes prior art in this field. In addition, a fast and physics-based inductor model is exploited to put the results contributed by many different groups in various technologies and achieved over the past eight years into perspective. Inductors are compared not only by their maximum quality factors (Q/sub max/), but also by taking the frequency at Q/sub max/, the inductance value (L), the self-resonance frequency (f/sub SR/), and the coil area into account. It is further explained that the spiral coil structure on a lossy silicon substrate can operate in three different modes, depending at first order on the silicon doping concentration. Ranging from high to low substrate resistivity, inductor-mode, resonator-mode, and eddy-current regimes are defined by characteristic changes of Q/sub max/, L, and f/sub SR/. The advantages and disadvantages of patterned or blanket resistive ground shields between the inductor coil and substrate and the effect of a substrate contact on the inductor are also addressed in this paper. Exploring optimum inductor designs under various constraints leverages the speed of the model. Finally, in view of the continuously increasing operating frequencies in advancing to new generations of RF systems, the range of feasible inductance values for given quality factors are predicted on the basis of optimum technological features.

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On the design of RF spiral inductors on silicon

The recent advances in 60-GHz radios have called for the parallel development of compact and efficient millimeter-wave antennas. This brief addresses for the first time the design, fabrication, and characterization of on-chip inverted-F and quasi-Yagi antennas for 60-GHz radios. The design was made using the Zeland IE3D software package. The fabrication was realized with the back-end-of-line process of silicon substrates of low resistivity 10 /spl Omega//spl middot/cm. The characterization was conducted on wafer with Cascade Microtech coplanar probes and an HP8510XF network analyzer. The results show that the inverted-F antenna achieved a minimum return loss of 32 dB and a gain of -19 dBi at 61 GHz; while the quasi-Yagi antenna achieved a minimum return loss of 6.75 dB and a gain of -12.5 dBi at 65 GHz. Good agreement has been observed between the measured and simulated results.

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On-chip antennas for 60-GHz radios in silicon technology

The BOSCH etch process, which is commonly used in microelectromechanical system fabrication, has been extensively investigated in this work for implementation in through-silicon via (TSV) technology for 3D-microsystems packaging. The present work focuses on thermo-mechanical stresses caused by thermal loading due to post-TSV processes and their impact on the electrical performance of through-silicon copper interconnects. A test vehicle with deep silicon copper-plated comb structure was designed to study and evaluate different deep silicon via etch processes and its effect on the electrical leakage characteristics under various electrical and thermal stress conditions. It has been shown that the leakage current between the comb interconnect structures increases with an increase in sidewall roughness and that it can be significantly lowered by smoothening the sidewalls. It was also shown that by tailoring a non-BOSCH etch process with the normal BOSCH process, a similar leakage current reduction can be achieved. It was also shown through thermo-mechanical simulation studies that there is a clear correlation between high leakage current behavior due to non-uniform Ta barrier deposition over the rough sidewalls and the thermo-mechanical stress induced by post-TSV processes.

http://iopscience.iop.org/article/10.1088/0960-1317/18/7/075018/pdf

A study of thermo-mechanical stress and its impact on through-silicon vias

Various types of glass substrates have been compared with respect to their suitability as a low-loss substrate in waferlevel chipscale packaging for RF applications. Processability has been evaluated by fabrication of shallow and deep recesses using wet etching in HF (iHjP04) solutions. Electrical characteristics (dielectric constant and attenuation) have been extracted from measurements on coplanar wave guides (CPWs) up to 10 GHz. Results show that Coming Pyrex #7740 glass provides optical quality of wet-etched deep recesses, but exhibit about 2 times higher electrical attenuation than Hoya SD-2. Pyrex #7740 and SD-2 are thermally matched to silicon and due to some alkali content, they are suitable for anodic bonding. The relatively high content of A120j (-20%) in SD-2 is favorable for its electrical properties, but makes wet etching of deep recesses more difficult. The non-alkaline AF45, with C'IE almost 2 times of Si (CTEm45=4.5x106 K'), is suitable for adhesive bonding and is difficult to pattern using wet etching. Its electrical attenuation is close to that of SD-2. The measured dielectric constants (at 6 GHz) for SD-2, F'yrex #7740 and AF45 are 4.7,5.9 and 6.1, respectively. Introdnetion

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Processability and electrical characteristics of glass substrates for RF wafer-level chip-scale packages

This paper reports on fabrication and design considerations of an integrated folded shorted-patch chip-size antenna for applications in shortrange wireless microsystems and operating inside the 5–6 GHz ISM band. Antenna fabrication is based on wafer-level chip-scale packaging (WLCSP) techniques and consists of two adhesively bonded glass wafers with patterned metallization and through-wafer electrical interconnects. Via formation in glass substrates is identified as the key fabrication step. Various options for via formation are compared and from these, a 193 nm excimer laser ablation is selected for fabrication of the antenna demonstrator. The fabricated antenna has dimensions of 4 mm × 4m m× 1 mm, measured operating frequency of 5.05 GHz with a bandwidth of ∼200 MHz at the return loss of −10 dB and a simulated radiation efficiency of 60% were achieved. © 2005 Elsevier B.V. All rights reserved.

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Integrated chip-size antennas for wireless microsystems: Fabrication and design considerations

High-resistivity polycrystalline silicon (HRPS) wafers are utilized as low-loss substrates for three-dimensional integration of on-chip antennas and RF passive components (e.g. large inductors) in wafer-level chip-scale packages (WLCSP). Sandwiching of HRPS and silicon wafers enables to integrate large RF passives with a spacing of >150 /spl mu/m to the conductive silicon substrate containing the circuitry, while providing mechanical stability, reducing form factor and avoiding any additional RF loss. Antenna performance comparable to glass substrates and high quality factors for large spiral inductors (Q=11 at 1 GHz; 34 nH) are demonstrated. The HRPS substrates have high dielectric constant, low RF loss, high thermal conductivity, perfect thermal matching, and processing similar to single-crystalline silicon.

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Wafer-level integration of on-chip antennas and RF passives using high-resistivity polysilicon substrate technology

Several techniques for fabrication of through-wafer vias in silicon have been compared in terms of achievable via diameter, shape and geometry and their influence on mechanical strength of silicon dies/wafers. The assessed techniques are: powder blasting, laser melt cutting, laser ablation, and deep reactive ion etching. The resolution of each method and influence on geometry was evaluated by fabrication of through-wafer holes and slots in 240 /spl mu/m-thick silicon wafers. The mechanical strength is measured using ring-on-ring (RoR) and four-point bending methods. Additional stress-relief post-processing was applied to improve mechanical strength. Comparing the performance of bipolar transistors, before and after fabrication of laser ablated vias, indicates that the electrically affected zone does not exceed 10-20 /spl mu/m around the via edge.

Comparison of via-fabrication techniques for through-wafer electrical interconnect applications

Add-on process modules as enhancements of standard high-frequency silicon integration processes are discussed. Such modules can be added without any interference with the core process before (pre-process modules), during (mid-process modules), or after (post-process modules) the circuit integration. High-resistivity silicon substrates, the patterned metal ground shield, and bulk micromachining are presented as examples in each category, respectively.

A. Polyakov

Papers

Processability and electrical characteristics of glass substrates for RF wafer-level chip-scale packages

Integrated chip-size antennas for wireless microsystems: Fabrication and design considerations

Wafer-level integration of on-chip antennas and RF passives using high-resistivity polysilicon substrate technology

Comparison of via-fabrication techniques for through-wafer electrical interconnect applications

Substrate options and add-on process modules for monolithic RF silicon technology