Disclosed is a coaxial type signal line that solves problems associated with signal interference and the connection of signal lines that are generated in a radio frequency (RF) electrical system. A method for manufacturing the coaxial type signal line includes the steps of forming a groove on a substrate, forming a first ground line on a surface of the groove and a plain surface of the substrate, forming a first dielectric layer including dielectric material on the first ground line formed on the surface of the groove, forming a signal line on the first dielectric layer the signal line for transmitting signals, forming a second dielectric layer including dielectric material on the signal line and the first dielectric layer, and forming a second ground line on the first ground line and the second dielectric layer. Since the signal line in the signal line structure according to the present invention is electrically shielded by the first and second ground lines, interference between the signal line and other signal lines on the semiconductor substrate can be prevented, and accordingly, the signal lines may be designed compactly on a semiconductor substrate and the system size can be reduced.

Coaxial type signal line and manufacturing method thereof

Today's competitive business environment imposes new challenges to manufacturing companies. For these companies to survive in this environment, implementing product lifecycle management (PLM) technologies with an emphasis on cost control is one valid approach. PLM is a strategic business approach that applies a consistent set of business solutions to help manufacturing companies manage all the activities related to a product in an integrated way across the lifecycle from customer need to product recycling and disposal. Product lifecycle cost is an important measure for PLM implementation. It can help track and analyze the financial information of activities associated with each phase of a product's lifecycle. The paper presents a framework of the product lifecycle costing system for supporting decision making, especially the decision making at very early stages of a product lifecycle. It can be used as a design support tool to help new product development. A number of methodologies and tools are developed in the system. The case based reasoning method is used to quickly build a new product model. The costs of product development processes related to the new product are calculated using activity based costing methods. Dynamic programming is then used to obtain an optimal set of product development processes with the objective of optimizing the overall product development cost. This system is built using object oriented modeling methods.

Framework of a Product Lifecycle Costing System

The excessive interconnection delay and fast increasing development cost, as well as complexity of the single-chip integration of different technologies, are likely to become the major stumbling blocks for the success of monolithic system-on-chips. To address the above problems, this paper investigates a new VLSI integration paradigm, the so-called 2.5-dimensional (2.5-D) integration scheme. Using this scheme, a VLSI system is implemented as a three-dimensional stacking of monolithic chips. A cost analysis framework was developed to justify the 2.5-D integration scheme from an economic point of view. Enabling technologies for the new integration scheme are also reviewed.

2.5-dimensional VLSI system integration

Passive components integrated into a high‐density substrate can be a tolerable way to overcome the size and manufacturing limits of SMD passives mounted on to the system board. Still, this technology is perceived as being “too risky” and not cost‐effective. In this paper we propose a “passive optimized” solution combining the advantages from both SMD and integrated technology and avoiding the respective drawbacks. Exemplified by a GPS receiver front end, we present a methodology to assess the possible benefits when using the mixed technology.

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Assessing the cost‐effectiveness of integrated passives

Continued technology scaling together with the integration of disparate technologies in a single chip means that device performance continues to outstrip interconnect and packaging capabilities, an ...

/pdf/system-interconnection-design-trade-offs-in-three-1adx2t25tk.pdf

System Interconnection Design Trade-offs in Three-Dimensional (3-D) Integrated Circuits

Today's high-density packaging technologies make early attention to most factors essential in the design of successful products. A process-oriented, scalable cost-modeling tool, the Modular Optimization Environment (MOE), enables a continuous cost-quality-performance trade-off analysis throughout the design and manufacturing process.

Modeling and optimizing the costs of electronic systems

Multi-Chip Module (MCM) technologies offer a wide variety of design options for the integration of electronics. However, a number of optimization problems have been reported in literature for the production of such highly complex circuits. One of the most well known problems is the dependence of module yield on the availability of so called Known-Good-Dies (KGDs). Hence, uncertainties about the quality level of the unpackaged (bare) dies available to the MCM manufacturer pose a number of questions concerning test, rework and die handling strategies. The cost and goodness methodologies introduced in this paper facilitate a thorough analysis and optimization of different possible MCM production flows. Moreover, the results generated demonstrate the power of the approach introduced.

CostAS-KGD process cost modeling

This paper presents recent investigations on a novel transmission line structure with improved RF-performance and increased shielding capability based on MCM-L interconnect technology. Three key issues are addressed: Maximization of usable interconnect bandwidth, reproducibility of the characteristic electrical properties in large-volume production, and minimization of inter-signal and electromagnetic interference. Thanks to recent improvements of MCM-L technology this new structure is processable in a cost-effective roll-to-roll production cycle. The electrical properties of the new structure are deduced from the well-known coaxial and triplate transmission line models. Furthermore, FEM-simulation results provide an estimation of the limitations of the proposed structure, which are caused by conductor and dielectric losses. The design of a test-vehicle intended for verification of the simulation results is presented. And finally, measurement results obtained from TDR/TDT and VNA measurement setups are reported and compared to the theoretical estimations.

http://ieeexplore.ieee.org/iel3/4291/12352/00569343.pdf

Investigations on novel coaxial transmission line structures on MCM-L

Laminated multi-chip-module technology (MCM-L) is well known for its cost effectiveness in large-volume applications. However, the implementation of advanced designs such as RF-analog or high-speed digital circuits suffers mainly from the large dielectric losses of the organic dielectric layers, conductor losses, and the manufacturing tolerances of state-of-the-art MCM-L technologies. However, if MCM-L substrate behaviour could be modelled and simulated more accurately, these drawbacks could be overcome. Indeed, the basis of accurate simulation results are precise electrical models of the interconnect. In this paper a theoretical analysis of typical MCM-L interconnects and measurements on MCM-L buildups are presented. Based on the measurement results, obtained mainly by TDR/TDT setups, it is demonstrated how MCM-L substrates can be a cost-effective solution for high-speed designs.

http://ieeexplore.ieee.org/iel3/4089/11988/00552440.pdf

MCM-L as a cost-effective solution for high-speed digital design

The well known Motorola Reliability Test Vehicle (MRTV) activities have only recently been transferred to the Interconnection Technology Research Institute (ITRI). In 1977, an improved version of the Motorola MRTV-2.2, now ITRI-TV2.4A, was manufactured. 18 technologically different samples were submitted by 16 manufacturers worldwide for testing. ITRI-TV2.4A has been designed to be compatible with all major classes of high density MCM-L technologies based on photo-defined, laser ablated, mechanically punched, and plasma etched via generation. Besides various reliability test structures that occupy most of the routing area, some space is reserved for dedicated RF test structures. The Electronics Lab of ETH Zurich is responsible for development and measurement of these structures. In this contribution, the suitability of the different technologies for high frequency designs is compared on the basis of key characteristics such as propagation delays and dielectric losses. These performance figures are derived form vector network analyzer (VNA) and time domain reflectometry (TDR) measurement set-ups. The paper gives a brief introduction into the special conditions for RF design on very thin laminate substrates. Then, a comprehensive summary of recent RF measurement results obtained from ITRI-TV2.4A is presented. The paper concludes with an overview of the developmental status of the involved major classes of MCM-L fabrication technology.

http://ieeexplore.ieee.org/iel4/5497/14778/00670748.pdf

A. Thiel

Papers

Modeling and optimizing the costs of electronic systems

CostAS-KGD process cost modeling

Investigations on novel coaxial transmission line structures on MCM-L

MCM-L as a cost-effective solution for high-speed digital design

A comparative analysis of RF-characteristics of high-density MCM-L technologies