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Abdolali Abdipour

Researcher at Amirkabir University of Technology

Publications -  292
Citations -  2244

Abdolali Abdipour is an academic researcher from Amirkabir University of Technology. The author has contributed to research in topics: Amplifier & Time domain. The author has an hindex of 20, co-authored 287 publications receiving 1859 citations. Previous affiliations of Abdolali Abdipour include École Normale Supérieure & Supélec.

Papers
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Journal ArticleDOI

Compact Microstrip Wilkinson Power Dividers With Harmonic Suppression and Arbitrary Power Division Ratios

TL;DR: In this paper, a Wilkinson power divider on a single-layer microstrip line that can reduce the occupied area, suppress the harmonic components, and/or provide the arbitrary power division ratios is described.
Journal ArticleDOI

A Very Compact Ultrawideband Printed Omnidirectional Monopole Antenna

TL;DR: In this paper, a microstrip-fed monopole antenna with truncated ground plane is presented, where three notches with proper sizes and positions in two corners of the quasi-square radiating patch are inserted.
Journal ArticleDOI

Integrated Millimeter-Wave Wideband End-Fire 5G Beam Steerable Array and Low-Frequency 4G LTE Antenna in Mobile Terminals

TL;DR: The novelty of this paper is the collocation of a high- frequencies end-fire 5G antenna array with an old-generation low-frequency antenna, such as 4G in small space in the mobile terminal, without interfering with the radiation pattern and impedance matching of both low- and high-frequency antennas.
Proceedings ArticleDOI

A single feed dual-band circularly polarized millimeter-wave antenna for 5G communication

TL;DR: In this article, a monolayer circularly polarized patch antenna is considered without any 90° phase shifter and is excited by a single-feed microstrip line, which is very desirable for high gain antenna array implementation in millimeter wave band in order to compensate the link loss.
Journal ArticleDOI

A 33-GHz LNA for 5G Wireless Systems in 28-nm Bulk CMOS

TL;DR: This brief presents a design procedure of a compact 33-GHz low-noise amplifier (LNA) for fifth generation (5G) applications realized in 28-nm LP CMOS, with emphasis on the optimization of design and layout techniques for active and passive components in the presence of rigorous metal density rules and other back-end-of-the-line challenges.