Data centers are critical, energy-hungry infrastructures that run large-scale Internet-based services. Energy consumption models are pivotal in designing and optimizing energy-efficient operations to curb excessive energy consumption in data centers. In this paper, we survey the state-of-the-art techniques used for energy consumption modeling and prediction for data centers and their components. We conduct an in-depth study of the existing literature on data center power modeling, covering more than 200 models. We organize these models in a hierarchical structure with two main branches focusing on hardware-centric and software-centric power models. Under hardware-centric approaches we start from the digital circuit level and move on to describe higher-level energy consumption models at the hardware component level, server level, data center level, and finally systems of systems level. Under the software-centric approaches we investigate power models developed for operating systems, virtual machines and software applications. This systematic approach allows us to identify multiple issues prevalent in power modeling of different levels of data center systems, including: i) few modeling efforts targeted at power consumption of the entire data center ii) many state-of-the-art power models are based on a few CPU or server metrics, and iii) the effectiveness and accuracy of these power models remain open questions. Based on these observations, we conclude the survey by describing key challenges for future research on constructing effective and accurate data center power models.

Data Center Energy Consumption Modeling: A Survey

Dynamic energy-aware cloudlet-based mobile cloud computing model for green computing

In-band full-duplex (IBFD) technology can enable unique system capabilities and network architectures by allowing devices to transmit and receive on the same frequency at the same time. While previously considered impossible, this ability can now be used to optimize resource sharing within the crowded frequency spectrum for various communication systems, including 5G new radio. The potential of these IBFD systems can only be realized if each device incorporates a sufficient number of self-interference cancellation techniques to ensure that its receivers do not saturate. This tutorial survey offers the most comprehensive collection to date of these techniques and discusses how all of them can be implemented within the different domains of a typical transceiver. In addition, the results of a novel IBFD system study are presented for more than 50 demonstrated communication systems with more than 80 different measurement scenarios. The various system parameters are then combined into a new figure of merit, which can be used to propel future research and accelerate the inclusion of IBFD technology within an upcoming wireless standard.

In-Band Full-Duplex Technology: Techniques and Systems Survey

Cloud computing is today’s most emphasized Information and Communications Technology (ICT) paradigm that is directly or indirectly used by almost every online user. However, such great significance comes with the support of a great infrastructure that includes large data centers comprising thousands of server units and other supporting equipment. Their share in power consumption generates between 1.1p and 1.5p of the total electricity use worldwide and is projected to rise even more. Such alarming numbers demand rethinking the energy efficiency of such infrastructures. However, before making any changes to infrastructure, an analysis of the current status is required. In this article, we perform a comprehensive analysis of an infrastructure supporting the cloud computing paradigm with regards to energy efficiency. First, we define a systematic approach for analyzing the energy efficiency of most important data center domains, including server and network equipment, as well as cloud management systems and appliances consisting of a software utilized by end users. Second, we utilize this approach for analyzing available scientific and industrial literature on state-of-the-art practices in data centers and their equipment. Finally, we extract existing challenges and highlight future research directions.

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Cloud Computing: Survey on Energy Efficiency

Android Open Source Projectを対象としたパッチレビュー活動の調査

Fifth-generation cellular communication standards (5G) target Gb/s data-rates, pushing the industry beyond the sub-6GHz bands. Tens of GHz of spectrum are available in the frequency bands from 30 to 300GHz. To maintain acceptable link budgets with sufficient antenna apertures, arrays are typically required at these frequencies and electrical beam steering is needed to retain spatial coverage. For such complex systems, highly-integrated, low-cost and energy-efficient SoCs are desirable to enable volume deployment. FinFET technologies are an ideal candidate to tackle this challenging integration, given the excellent balance between density and RF/mm-wave performance that has been recently demonstrated [1].

9.7 A Scalable 71-to-76GHz 64-Element Phased-Array Transceiver Module with 2×2 Direct-Conversion IC in 22nm FinFET CMOS Technology

Demonstrations of mm-Wave arrays with >50 elements in silicon has led to an interest in large-scale mm-Wave MIMO arrays for 5G networks, which promise substantial improvements in network capacity [1,2]. Practical considerations result in such arrays being developed with a tiled approach, where N unit cells with M elements each are tiled to achieve large MIMO/phased arrays with NM elements [2]. Achieving stringent phase-noise specifications and scalable LO distribution to maintain phase coherence across different unit cell ICs/PCBs are a critical challenge. In this paper, we demonstrate a scalable, single-wire-synchronization architecture and circuits for mm-Wave arrays that preserve the simplicity of daisy-chained LO distribution, compensate for phase offset due to interconnects, and provide phase-noise improvement with increasing number of PLLs [3]. Measurements on a scalable 28GHz prototype demonstrate a 21% improvement in rms jitter and a 3.4dB improvement in phase noise at 10MHz offset when coupling 28GHz PLLs across three different ICs.

2.2 A scalable 28GHz coupled-PLL in 65nm CMOS with single-wire synchronization for large-scale 5G mm-wave arrays

Software behavior can significantly affect computer energy efficiency in everything from small devices up to servers in data centers. However, there are multiple techniques that software developers can use to reduce the energy consumption of drivers and applications.

Enabling Green IT through Energy-Aware Software

This paper extends N-path filtering to the code domain by proposing code-modulated local oscillator signals. A correlator-based perspective of N-path mixer receiver (RX) is presented to demonstrate interferer-rejection and desired signal reception in a code-domain N-path RX. Pairs of Walsh-function-based codes are proposed for modulating desired RX and known interferers [such as self-interference (SI) from transmitter (TX)] to achieve high interferer rejection. An N-path architecture for concurrent reception of two code-modulated signals is also presented. A 0.3–1.4-GHz 65-nm CMOS implementation achieves 35-dB gain for desired signals and concurrently receives two RX signals while rejecting mismatched spreading codes at RF input. The proposed TX SI mitigation approach results in 38.5-dB rejection for −11.8 dBm 1.46-Mb/s quadrature phase-shift keying (QPSK) modulated SI at the RX input. The RX achieves 23.7-dBm output referred 1dB gain compression (OP1dB) for in-band SI, while consuming ~35 mW and occupies 0.31 mm2. Such code-domain selection/rejection can be used in conjunction with other N-path filtering schemes for signal selection/rejection based on a combination of spatial, spectral, and code-domain properties.

An Interferer-Tolerant CMOS Code-Domain Receiver Based on N-Path Filters

Integrated oscillators with octave frequency tuning range (FTR) are desirable for wireless transceivers supporting multiple frequency bands. In this paper, we describe a wide-FTR CMOS voltage-controlled oscillator (VCO) based on a novel area-efficient series resonator mode-switching scheme that preserves resonator quality factor $Q$ across the entire octave tuning range. This allows the CMOS VCO to simultaneously achieving wide FTR, area efficiency, and low phase noise, demonstrating state-of-the-art figure of merit (FoM) for > 10-GHz octave-tuning range VCOs. We also analyze the relationship between $Q$ and FTR across common resonator band-switching schemes, quantifying performance limits and highlighting the benefits of using mode-switching for wide-FTR VCOs. The proposed approach is demonstrated through a 6.4–14-GHz (74.6% FTR) VCO implemented in 65-nm CMOS that achieves 186–188-dB VCO FoM, demonstrating good FoM across the entire FTR. The scalability of this approach toward achieving even larger FTR is also demonstrated by a triple-mode 2.2–8.7-GHz (119% FTR) CMOS VCO. Area efficiency of the proposed mode-switching scheme is demonstrated by the state-of-the-art 197-dB FoM area achieved by the 14-GHz VCO.

Abhishek Agrawal

Papers

9.7 A Scalable 71-to-76GHz 64-Element Phased-Array Transceiver Module with 2×2 Direct-Conversion IC in 22nm FinFET CMOS Technology

2.2 A scalable 28GHz coupled-PLL in 65nm CMOS with single-wire synchronization for large-scale 5G mm-wave arrays

Enabling Green IT through Energy-Aware Software

An Interferer-Tolerant CMOS Code-Domain Receiver Based on N-Path Filters

Series Resonator Mode Switching for Area-Efficient Octave Tuning-Range CMOS $LC$ Oscillators