This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

In this paper, a receiver front-end tailored to Bluetooth Low Energy applications is presented. In the proposed solution, the LNA, mixers, VCO, quadrature scheme and the first stage of the analog base-band share the same bias current under a 0.8 V voltage supply leading to a sub-mW power consumption. A channel selection filter, implemented through a current re-use gm-C topology, completes the design. The presented prototype, realized in 130 nm CMOS technology, occupies an active area of 0.25 mm $^{2}$ while consuming only 0.6 mW. With a NF of 15.8 dB, an IIP3 of $-$ 17 dBm at the maximum gain and an image rejection above 30 dB the receiver front-end meets BLE noise figure, image rejection, phase noise and linearity requirements.

Sub-mW Current Re-Use Receiver Front-End for Wireless Sensor Network Applications

High-rate communications technology leveraging the unlicensed spectrum around 60 GHz is almost ready for deployment with several demonstrations of successful wireless links. One key aspect of the transceiver is the ability to handle analog fractional bandwidths in the order of 20%, challenging for both the linear processing chain and the frequency reference generator. In classical LC loaded stages bandwidth trades with gain making them unsuitable for wide band amplifiers at millimeter-waves where the available device gain is relatively low. In this work, we exploit inter-stage coupling realizing higher order filters where wider bandwidth is achieved at the expense of in-band gain ripple only. The receiver adopts a sliding IF architecture employing an integer-N type-II synthesizer, with a three state phase frequency detector charge pump combination, a switched tuned LC VCO followed by a low power wide range divider chain. By judicious choice of charge pump current and filter components integrated phase noise, critical for signal constellation integrity at high rate, is kept low. This paper inspects the inter-stage coupling technique, providing design formulas, and discusses the design of each receiver block. Experiments performed on 65 nm prototypes provide: 6.5 dB maximum noise figure over >;13 GHz bandwidth, -22.5 dBc integrated phase noise while consuming 84 mW.

A Wideband Receiver for Multi-Gbit/s Communications in 65 nm CMOS

A 2.4 GHz ZigBee receiver unifying a balun-LNA-I/Q-mixer (Blixer) and a baseband (BB) hybrid filter in one cell is fabricated in 65 nm CMOS. Without any external components, wideband input matching and passive pre-gain are concurrently achieved via co-optimizing an integrated low-Q network with a balun-LNA. The latter also features active-gain boosting and partial-noise canceling to enhance the gain and noise figure (NF). Above the balun-LNA are I/Q double-balanced mixers driven by a 4-phase 25% LO for downconversion and gain-phase balancing. The generated BB currents are immediately filtered by an IF-noise-shaping current-mode Biquad and a complex-pole load, offering first-order image rejection and third-order channel selection directly atop the Blixer. Together with other BB and LO circuitries, the receiver measures 8.5 dB NF, 57 dB gain and $-$ 6-dBm IIP3 $_{{\rm out}\mathchar"702D{\rm band}}$ at 1.7 mW power and 0.24 mm $^{2}$ die size. The S $_{11}$ -bandwidth ( ${ 10 dB) covers 2.25 to 3.55 GHz being robust to packaging variations. Most performance metrics compare favorably with the state-of-the-art.

A 2.4 GHz ZigBee Receiver Exploiting an RF-to-BB-Current-Reuse Blixer + Hybrid Filter Topology in 65 nm CMOS

A fully integrated CMOS GPS receiver RF front-end is presented. Systematic circuit optimizations for ultra-low voltage operation including subthreshold biasing, a novel mixer-VCO interface, and charge neutralization enable the supply voltage to be dramatically reduced as a means to save power. The 250 mV supply is the lowest ever reported for any integrated receiver RF front-end to date. Its 352 μW power consumption represents a three times power savings compared to the prior lowest GPS receiver RF front-ends reported in the literature. The prototype was fabricated in a 1P8M 130 nm CMOS process and includes a variable gain LNA, a quadrature VCO, quadrature mixers, and all required bias circuitry. The system has a measured gain of 42 dB, a noise figure of 7.2 dB, and an oscillator phase noise of - 112.4 dBc/Hz at a 1 MHz offset, resulting in a VCO FoM of 187.4 dBc/Hz.

A 250 mV, 352 $\mu$ W GPS Receiver RF Front-End in 130 nm CMOS

A fully integrated CMOS GPS receiver RF front-end is presented. Systematic circuit optimizations for ultra-low voltage operation including subthreshold biasing, a novel mixer-VCO interface, and charge neutralization enable the supply voltage to be dramatically reduced as a means to save power. The 250 mV supply is the lowest ever reported for any integrated receiver RF front-end to date. Its 352 μW power consumption represents a three times power savings compared to the prior lowest GPS receiver RF front-ends reported in the literature. The prototype was fabricated in a 1P8M 130 nm CMOS process and includes a variable gain LNA, a quadrature VCO, quadrature mixers, and all required bias circuitry. The system has a measured gain of 42 dB, a noise figure of 7.2 dB, and an oscillator phase noise of —112.4 dBc/Hz at a 1 MHz offset, resulting in a VCO FoM of 187.4 dBc/Hz.

A 250 mV, 352 μW GPS Receiver RF Front-End in 130 nm CMOS

A fully integrated CMOS GPS receiver RF front-end is presented. Systematic circuit optimizations for ultra-low voltage operation including subthreshold biasing, a novel mixer-VCO in- terface, and charge neutralization enable the supply voltage to be dramaticallyreducedasameanstosavepower.The250mVsupply isthelowesteverreported foranyintegratedreceiverRFfront-end to date. Its 352 W power consumption represents a three times powersavingscomparedtothepriorlowestGPSreceiverRFfront- ends reported in the literature. The prototype was fabricated in a 1P8M 130 nm CMOS process and includes a variable gain LNA, a quadrature VCO, quadrature mixers, and all required bias cir- cuitry. The system has a measured gain of 42 dB, a noise figure of 7.2 dB, and an oscillator phase noise of 112.4 dBc/Hz at a 1 MHz offset, resulting in a VCO FoM of 187.4 dBc/Hz.

A 250 mV, 352 W GPS Receiver RF Front-End

A low-IF quadrature GPS receiver consisting of a VCO, mixer and variable gain LNA is implemented in 130 nm CMOS. Consuming 352 µW from a 250 mV supply, it has the lowest supply voltage for an integrated receiver reported to date. The measured noise figure is 7.2 dB with a gain of 42 dB at a 10 MHz IF frequency. At a 1 MHz offset, the VCO phase noise is −112.4 dBc/Hz, resulting in an FoM of 187.4 dBc/Hz.

Adam C. Heiberg

Papers

A 250 mV, 352 $\mu$ W GPS Receiver RF Front-End in 130 nm CMOS

A 250 mV, 352 μW GPS Receiver RF Front-End in 130 nm CMOS

A 250 mV, 352 W GPS Receiver RF Front-End

A 250 mV, 352 µW low-IF quadrature GPS receiver in 130 nm CMOS