Modern computers are based on the von Neumann architecture in which computation and storage are physically separated: data are fetched from the memory unit, shuttled to the processing unit (where computation takes place) and then shuttled back to the memory unit to be stored. The rate at which data can be transferred between the processing unit and the memory unit represents a fundamental limitation of modern computers, known as the memory wall. In-memory computing is an approach that attempts to address this issue by designing systems that compute within the memory, thus eliminating the energy-intensive and time-consuming data movement that plagues current designs. Here we review the development of in-memory computing using resistive switching devices, where the two-terminal structure of the devices, their resistive switching properties, and direct data processing in the memory can enable area- and energy-efficient computation. We examine the different digital, analogue, and stochastic computing schemes that have been proposed, and explore the microscopic physical mechanisms involved. Finally, we discuss the challenges in-memory computing faces, including the required scaling characteristics, in delivering next-generation computing. This Review Article examines the development of in-memory computing using resistive switching devices.

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In-memory computing with resistive switching devices

Electronics is approaching a major paradigm shift because silicon transistor scaling no longer yields historical energy-efficiency benefits, spurring research towards beyond-silicon nanotechnologies. In particular, carbon nanotube field-effect transistor (CNFET)-based digital circuits promise substantial energy-efficiency benefits, but the inability to perfectly control intrinsic nanoscale defects and variability in carbon nanotubes has precluded the realization of very-large-scale integrated systems. Here we overcome these challenges to demonstrate a beyond-silicon microprocessor built entirely from CNFETs. This 16-bit microprocessor is based on the RISC-V instruction set, runs standard 32-bit instructions on 16-bit data and addresses, comprises more than 14,000 complementary metal–oxide–semiconductor CNFETs and is designed and fabricated using industry-standard design flows and processes. We propose a manufacturing methodology for carbon nanotubes, a set of combined processing and design techniques for overcoming nanoscale imperfections at macroscopic scales across full wafer substrates. This work experimentally validates a promising path towards practical beyond-silicon electronic systems. A 16-bit microprocessor built from over 14,000 carbon nanotube transistors may enable energy efficiency advances in electronics technologies beyond silicon.

Modern microprocessor built from complementary carbon nanotube transistors

Approximate computing is an emerging approach for reducing the energy consumption and design complexity in many applications where accuracy is not a crucial necessity. In this study, ultra-efficient imprecise 4:2 compressor and multiplier circuits as the building blocks of the approximate computing systems are proposed. The proposed compressor uses only one majority gate which is different from the conventional design methods using AND - OR and XOR logics. Furthermore, the majority gate is the fundamental logic block in many of the emerging majority-friendly nanotechnologies such as quantum-dot cellular automata ( QCA ) and single-electron transistor ( SET ). The proposed circuits are designed using FinFET as a current industrial technology and are simulated with HSPICE at 7nm technology node. The results indicate that our imprecise compressor is superior to its previous counterparts in terms of delay, power consumption, power delay product (PDP) and area, and improves these parameters on average by 32%, 68%, 78%, and 66%, respectively. In addition, the proposed efficient approximate multiplier is utilized in image multiplying as an important image processing application. The HSPICE and MATLAB simulations indicate that the proposed inexact multiplier provides a significant compromise between accuracy and design efficiency for approximate computing.

A Majority-Based Imprecise Multiplier for Ultra-Efficient Approximate Image Multiplication

Continued improvement in computing efficiency requires functional specialization of hardware designs. Agile hardware design methodologies have been proposed to alleviate the increased design costs of custom silicon architectures, but their practice thus far has been accompanied with challenges in integration and validation of complex systems-on-a-chip (SoCs). We present the Chipyard framework, an integrated SoC design, simulation, and implementation environment for specialized compute systems. Chipyard includes configurable, composable, open-source, generator-based IP blocks that can be used across multiple stages of the hardware development flow while maintaining design intent and integration consistency. Through cloud-hosted FPGA accelerated simulation and rapid ASIC implementation, Chipyard enables continuous validation of physically realizable customized systems.

Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs

We compare the performance of static random access memory (SRAM) cells based on negative capacitance (NC) FinFETs and reference FinFETs at the 7-nm technology node. We use a physics-based model for NC FinFETswhere we couple the Landau–Khalatnikovmodel of ferroelectric materials with the standard BSIM-CMG model of FinFET. For the reference FinFETs, we use the predictive model parameters optimized for SRAM design as per the ASAP7 PDK. We exploit the unique characteristics of NC-FinFETs and demonstrate that for ferroelectric thickness below a critical value, SRAMs with higher hold and read stability, better write-ability, lower leakage as well as faster read access time can be designed at the cost of increased write delay.

Performance Evaluation of 7-nm Node Negative Capacitance FinFET-Based SRAM

https://cyberleninka.org/article/n/1380904.pdf

ASAP7: A 7-nm finFET predictive process design kit

A MIPS 4Kc compliant embedded microprocessor design that incorporates architectural features for software controlled soft-error recovery is presented. The design leverages classical fault tolerance techniques, e.g., error detection and instruction restart, implemented at the micro-architectural level, and added instructions for error recovery. Soft-errors are detected as the instructions commit to architectural state. At this point, an exception is taken and software recovers the correct machine state and restarts execution. The software recovery allows full machine inspection to determine error root causes. Added instructions also facilitate silicon validation of the hardware and software recovery mechanisms. The design is implemented in a commercial low standby power 90-nm bulk CMOS process and the prototype operates at up to 336 MHz. Finally, proton broad beam irradiation results are presented. The processor demonstrates correct recovery, resuming program operation, from over 500 detected soft-errors, with no unrecoverable errors.

A Soft-Error Mitigated Microprocessor With Software Controlled Error Reporting and Recovery

This work describes voting feedback circuits for triple modular redundant (TMR) self-correcting flip-flops that reduce the flip-flop circuit area by 20% and the energy consumption by 10% over the conventional use of a majority gate. A fully pipelined 256-bit key and 128-bit data advanced encryption standard (AES) engine implemented at the 90 nm technology node using the proposed design and has a maximum performance of 400 MHz and 297 mW in TMR and multi-thread modes. It operates in a low-power, non-redundant mode at 102 mW power dissipation. Testability modes are are also described.

Muller C-element Self-corrected Triple Modular Redundant Logic with Multithreading and Low Power Modes

Register file (RF) memory is important in low power SOCs due to its inherent low voltage stability. Moreover, designs increasingly use compiled instead of custom memory blocks, which frequently employ static, rather than pre-charged dynamic register files. In this paper, we compare static and dynamic RF power dissipation and timing characteristics. The relative timing and power advantages of the designs are shown to be dependent on the memory aspect ratio, i.e. array width and height. One version, fabricated on a foundry bulk CMOS 90-nm low standby power (LP) process provides a baseline for the analyses.

Delay and power tradeoffs for static and dynamic register files

An integrated methodology combining redundant clock tree synthesis and pulse clocked latches mitigates both SEU and SET with reduced power consumption. The approach utilizes commercial CAD tools. An advanced encryption system is implemented with the proposed design is compared to a previous design with non-redundant clock trees and local delay generation. The proposed approach reduces energy per operation by 18% over an improved version of the prior approach, with negligible area impact.

Aditya Gujja

Papers

ASAP7: A 7-nm finFET predictive process design kit

A Soft-Error Mitigated Microprocessor With Software Controlled Error Reporting and Recovery

Muller C-element Self-corrected Triple Modular Redundant Logic with Multithreading and Low Power Modes

Delay and power tradeoffs for static and dynamic register files

Redundant Skewed Clocking of Pulse-Clocked Latches for Low Power Soft Error Mitigation