ASAP7: A 7-nm finFET predictive process design kit
Lawrence T. Clark,Vinay Vashishtha,Lucian Shifren,Aditya Gujja,Saurabh Sinha,Brian Cline,Chandarasekaran Ramamurthy,Greg Yeric +7 more
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TLDR
A high density, low-power standard cell architecture, developed using design/technology co-optimization (DTCO), as well as example SRAM cells are shown, and the PDK transistor electrical assumptions are explained, as are the FEOL and BEOL design rules.About:
This article is published in Microelectronics Journal.The article was published on 2016-07-01 and is currently open access. It has received 326 citations till now. The article focuses on the topics: Multiple patterning & Front end of line.read more
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In-memory computing with resistive switching devices
TL;DR: This Review Article examines the development of in-memory computing using resistive switching devices, where the two-terminal structure of the devices, theirresistive switching properties, and direct data processing in the memory can enable area- and energy-efficient computation.
Journal ArticleDOI
Modern microprocessor built from complementary carbon nanotube transistors
Gage Hills,Christian Lau,Andrew Wright,Samuel H. Fuller,Mindy D. Bishop,Tathagata Srimani,Pritpal Kanhaiya,Rebecca Ho,Aya G. Amer,Yosi Stein,Denis Murphy,Arvind,Anantha P. Chandrakasan,Max M. Shulaker +13 more
TL;DR: This work experimentally validates a promising path towards practical beyond-silicon electronic systems and proposes a manufacturing methodology for carbon nanotubes, a set of combined processing and design techniques for overcoming nanoscale imperfections at macroscopic scales across full wafer substrates.
Journal ArticleDOI
A Majority-Based Imprecise Multiplier for Ultra-Efficient Approximate Image Multiplication
TL;DR: This study proposes an ultra-efficient imprecise 4:2 compressor and multiplier circuits as the building blocks of the approximate computing systems and indicates that the proposed inexact multiplier provides a significant compromise between accuracy and design efficiency for approximate computing.
Journal ArticleDOI
Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs
Alon Amid,David Biancolin,Abraham Gonzalez,Daniel Grubb,Sagar Karandikar,Harrison Liew,Albert Magyar,Howard Mao,Albert Ou,Nathan Pemberton,Paul Rigge,Colin Schmidt,John Wright,Jerry Zhao,Yakun Sophia Shao,Krste Asanovic,Borivoje Nikolic +16 more
TL;DR: The Chipyard framework is presented, an integrated SoC design, simulation, and implementation environment for specialized compute systems, that includes configurable, composable, open-source, generator-based IP blocks that can be used across multiple stages of the hardware development flow while maintaining design intent and integration consistency.
Journal ArticleDOI
Performance Evaluation of 7-nm Node Negative Capacitance FinFET-Based SRAM
Tapas Dutta,Girish Pahwa,Amit Ranjan Trivedi,Saurabh Sinha,Amit Agarwal,Yogesh Singh Chauhan +5 more
TL;DR: It is demonstrated that for ferroelectric thickness below a critical value, SRAMs with higher hold and read stability, better write-ability, lower leakage as well as faster read access time can be designed at the cost of increased write delay.
References
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Book
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TL;DR: In this article, the authors present a characterization of the resistivity of a two-point-versus-four-point probe in terms of the number of contacts and the amount of contacts in the probe.
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A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors
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A 14nm logic technology featuring 2 nd -generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size
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TL;DR: In this paper, a 14nm logic technology using 2nd-generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-gapped interconnects at performance-critical layers is described.
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