http://wpage.unina.it/valerio.persico/pubs/CloudIoT_FGCS.pdf

Integration of Cloud computing and Internet of Things

Modern computers are based on the von Neumann architecture in which computation and storage are physically separated: data are fetched from the memory unit, shuttled to the processing unit (where computation takes place) and then shuttled back to the memory unit to be stored. The rate at which data can be transferred between the processing unit and the memory unit represents a fundamental limitation of modern computers, known as the memory wall. In-memory computing is an approach that attempts to address this issue by designing systems that compute within the memory, thus eliminating the energy-intensive and time-consuming data movement that plagues current designs. Here we review the development of in-memory computing using resistive switching devices, where the two-terminal structure of the devices, their resistive switching properties, and direct data processing in the memory can enable area- and energy-efficient computation. We examine the different digital, analogue, and stochastic computing schemes that have been proposed, and explore the microscopic physical mechanisms involved. Finally, we discuss the challenges in-memory computing faces, including the required scaling characteristics, in delivering next-generation computing. This Review Article examines the development of in-memory computing using resistive switching devices.

/pdf/in-memory-computing-with-resistive-switching-devices-1mv368csjy.pdf

In-memory computing with resistive switching devices

The development of silicon semiconductor technology has produced breakthroughs in electronics—from the microprocessor in the late 1960s to early 1970s, to automation, computers and smartphones—by downscaling the physical size of devices and wires to the nanometre regime. Now, graphene and related two-dimensional (2D) materials offer prospects of unprecedented advances in device performance at the atomic limit, and a synergistic combination of 2D materials with silicon chips promises a heterogeneous platform to deliver massively enhanced potential based on silicon technology. Integration is achieved via three-dimensional monolithic construction of multifunctional high-rise 2D silicon chips, enabling enhanced performance by exploiting the vertical direction and the functional diversification of the silicon platform for applications in opto-electronics and sensing. Here we review the opportunities, progress and challenges of integrating atomically thin materials with silicon-based nanosystems, and also consider the prospects for computational and non-computational applications. Progress in integrating atomically thin two-dimensional materials with silicon-based technology is reviewed, together with the associated opportunities and challenges, and a roadmap for future applications is presented.

Graphene and two-dimensional materials for silicon technology.

IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

This paper will review emerging non-volatile memory (NVM) technologies, with the focus on phase change memory (PCM), spin-transfer-torque random-access-memory (STTRAM), resistive random-access-memory (RRAM), and ferroelectric field-effect-transistor (FeFET) memory. These promising NVM devices are evaluated in terms of their advantages, challenges, and applications. Their performance is compared based on reported parameters of major industrial test chips. Memory selector devices and cell structures are discussed. Changing market trends toward low power ( e.g. , mobile, IoT) and data-centric applications create opportunities for emerging NVMs. High-performance and low-cost emerging NVMs may simplify memory hierarchy, introduce non-volatility in logic gates and circuits, reduce system power, and enable novel architectures. Storage-class memory (SCM) based on high-density NVMs could fill the performance and density gap between memory and storage. Some unique characteristics of emerging NVMs can be utilized for novel applications beyond the memory space, e.g. , neuromorphic computing, hardware security, etc . In the beyond-CMOS era, emerging NVMs have the potential to fulfill more important functions and enable more efficient, intelligent, and secure computing systems.

A review of emerging non-volatile memory (NVM) technologies and applications

https://cyberleninka.org/article/n/1380904.pdf

ASAP7: A 7-nm finFET predictive process design kit

Predictive MOSFET models are critical for early stage design-technology co-optimization and circuit design research In this work, Predictive Technology Model files for sub-20nm multi-gate transistors have been developed (PTM-MG) Based on MOSFET scaling theory, the 2011 ITRS roadmap and early stage silicon data from published results, PTM for FinFET devices are generated for 5 technology nodes corresponding to the years 2012-2020 on the ITRS roadmap

Exploring sub-20nm FinFET design with predictive technology models

We live in an interconnected world. Computing power once reserved for server rooms now resides in our pockets. Tablets now outsell PCs. As marked as these changes have been, we are now entering a new era of vastly greater connectivity, where people interact with the world around them in entirely new ways. The Internet of Things is in its infancy, so predictions of precisely what it will become are dangerous, but several things are clear. First, the leaf nodes of the network will share some device and technology properties in terms of cost and computing capability, but also analog and wireless functionality. These nodes will interact with people and with the cloud. The “little data” of these interactions needs to integrate seamlessly with the “big data” of the world around them. The trust, security and service components of these interactions lead to further device and technology requirements. This talk looks at the trends and discusses some likely paths forward.

Device and technology implications of the Internet of Things

The Moore's Law era enjoyed a long run of lithographically-enabled pitch shrinking that directly reduced the cost per (von Neumann) function, as well as system power and performance improvements, via Dennard scaling. At the 50 year mark, the outlook for Moore's Law is muddier, as we encounter exponential complexity in MOS VLSI scaling and an increasing set of design limitations, including power limits, parasitics, variability, and of course cost. To continue to create compelling product scaling, we will increasingly require "all-of-the-above" advancements, more directly linking the MOS VLSI scaling to the circuits to the systems, in an era where future systems may be different than the computers we are familiar with.

Moore's law at 50: Are we planning for retirement?

Self-aligned double patterning (SADP) is being considered for use at the 10-nm technology node and below for routing layers with pitches down to $\boldsymbol {\sim }50$ nm because it has better line edge roughness and overlay control compared to other multiple patterning candidates. To date, most of the SADP-related literature has focused on enabling SADP-legal routing in physical design tools while few attempts have been made to address the impact SADP routing has on local, standard cell (SC) I/O pin access. At the same time, via layers are used to connect the local SADP routing layers to the I/O pins on lower metal layers. Due to the high via density on the Via-1 layer, the litho-etch-litho-etch (LELE)-aware Via-1 design becomes a necessity to achieve legal pin access at the SC level. In this paper, we present the first study on SADP-aware pin access and layout optimization at the SC level. Accounting for SADP-specific and Via-1 design rules, we propose a coherent framework that uses depth first search, mixed integer linear programming, and backtracking method to enable LELE friendly Via-1 design and simultaneously optimize SADP-based local pin access and within-cell connections. Our experimental results show that, compared with the conventional approach, our framework effectively improves pin access of the SCs and maximizes the pin access flexibility for routing.

Greg Yeric

Papers

ASAP7: A 7-nm finFET predictive process design kit

Exploring sub-20nm FinFET design with predictive technology models

Device and technology implications of the Internet of Things

Moore's law at 50: Are we planning for retirement?

Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization