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Akihiko Hashiguchi
Researcher at Sony Broadcast & Professional Research Laboratories
Publications - 27
Citations - 598
Akihiko Hashiguchi is an academic researcher from Sony Broadcast & Professional Research Laboratories. The author has contributed to research in topics: Signal & Clock signal. The author has an hindex of 9, co-authored 27 publications receiving 597 citations.
Papers
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Journal ArticleDOI
Dynamic Voltage and Frequency Management for a Low-Power Embedded Microprocessor
Takahiro Seki,Satoshi Akui,Katsunori Seno,Masakatsu Nakai,Tetsumasa Meguro,Tetsuo Kondo,Akihiko Hashiguchi,Hirokazu Kawahara,Kazuo Kumano,Masayuki Shimura +9 more
TL;DR: In this article, a dynamic voltage and frequency management (DVFM) scheme was introduced in a microprocessor for handheld devices with wideband embedded DRAM, which reduces the power consumption effectively by cooperation of the autonomous clock frequency control and the adaptive supply voltage control.
Journal ArticleDOI
Dynamic voltage and frequency management for a low-power embedded microprocessor
Masakatsu Nakai,S. Akui,Katsunori Seno,Tetsumasa Meguro,Takahiro Seki,Tetsuo Kondo,Akihiko Hashiguchi,Hirokazu Kawahara,K. Kumano,M. Shimura +9 more
TL;DR: A dynamic voltage and frequency management (DVFM) scheme with leakage power compensation effect is introduced in a microprocessor with 128-bit wideband 64-Mb embedded DRAM, achieving 82% power reduction in personal information management scheduler application and 40% power reduced in MPEG4 movie playback.
Patent
Power supply control device, semiconductor device and method of driving semiconductor device
TL;DR: In this paper, a delay detection circuit was proposed to detect the delay of the delay signal (outO0') with respect to the reference signal (Oi), and a supply voltage control circuit for controlling the supply voltage (VDD) supplied to the semiconductor circuit and the monitor circuit based on the result of detection.
Patent
Parallel processor apparatus having means for processing signals of different lengths
TL;DR: In this article, a parallel processor configured by a serial connection of a first parallel processor and a second parallel processor having n number of individual processors and (m-n) number of processors is presented.
Patent
Memory system and programming method thereof
TL;DR: In this article, a memory system and its programming method capable of reducing programming time for each page versatility is high, wherein the memory cell array is constituted, by a MONOS-type (MNOS) nonvolatile memory or floating gate non-volatile RAM.