Traditional adaptive methods that compensate for PVT variations need safety margins and cannot respond to rapid environmental changes. In this paper, we present a design (RazorII) which implements a flip-flop with in situ detection and architectural correction of variation-induced delay errors. Error detection is based on flagging spurious transitions in the state-holding latch node. The RazorII flip-flop naturally detects logic and register SER. We implement a 64-bit processor in 0.13 mum technology which uses RazorII for SER tolerance and dynamic supply adaptation. RazorII based DVS allows elimination of safety margins and operation at the point of first failure of the processor. We tested and measured 32 different dies and obtained 33% energy savings over traditional DVS using RazorII for supply voltage control. We demonstrate SER tolerance on the RazorII processor through radiation experiments.

RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance

In this paper, we present a dynamic voltage scaling (DVS) technique called Razor which incorporates an in situ error detection and correction mechanism to recover from timing errors. We also present the implementation details and silicon measurements results of a 64-bit processor fabricated in 0.18-/spl mu/m technology that uses Razor for supply voltage control. Traditional DVS techniques require significant voltage safety margins to guarantee computational correctness at the worst case combination of process, voltage and temperature conditions, leading to a loss in energy efficiency. In Razor-based DVS, however, the supply voltage is automatically reduced to the point of first failure using the error detection and correction mechanism, thereby eliminating safety margins while still ensuring correct operation. In addition, the supply voltage can be intentionally scaled below the point of first failure of the processor to achieve an optimal tradeoff between energy savings from further voltage reduction and energy overhead from increased error detection and correction activity. We tested and measured savings due to Razor DVS for 33 different dies and obtained an average energy savings of 50% over worst case operating conditions by scaling supply voltage to achieve a 0.1% targeted error rate, at a fixed frequency of 120 MHz.

A self-tuning DVS processor using delay-error detection and correction

We take advantage of these findings and propose a Razor II approach that introduces two components. First, instead of performing both error detection and correction in the FF, Razor II performs only detection in the FF, while correction is performed through architectural replay.

Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance

This paper describes the embedded feedback and control system on a 90-nm Itanium family processor, code-named Montecito, that maximizes performance while staying within a target power and temperature (PT) envelope. This system, referred to as Foxton Technology (FT), utilizes on-chip sensors and an embedded microcontroller to measure PT and modulate both voltage and frequency (VF) to optimize performance while meeting PT constraints. Changing both VF takes advantage of the cubic relationship of P/spl prop/CV/sup 2/F. We present measured results that show a 31% reduction in power for only a 10% drop in frequency. Montecito is able to implement FT using only 0.5% of the die area and 0.5% of the die power.

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Power and temperature control on a 90-nm Itanium family processor

This paper briefly reviews the forces that caused the power problem, the solutions that were applied, and what the solutions tell us about the problem As systems became more power constrained, optimizing the power became more critical; viewing power reduction from an optimization perspective provides valuable insights Section III describes these insights in more detail, including why Vdd and Vth have stopped scaling Section IV describes some of the low power techniques that have been used in the past in the context of the optimization framework This framework also makes it easy to see the impact of variability, which is discussed in more detail in section V along with the adaptive mechanisms that have been proposed and deployed to minimize the energy cost Section VI describes possible strategies for dealing with the slowdown in gate energy scaling, and the final section concludes by discussing the implications of these strategies for device designers

Scaling, power, and the future of CMOS

In this paper, a Dynamic Voltage and Frequency Management (DVFM) scheme introduced in a microprocessor for handheld devices with wideband embedded DRAM is reported. Our DVFM scheme reduces the power consumption effectively by cooperation of the autonomous clock frequency control and the adaptive supply voltage control. The clock frequency is controlled using hardware activity information to determine the minimum value required by the current processor load. This clock frequency control is realized without special power management software. The supply voltage is controlled according to the delay information provided from a delay synthesizer circuit, which consists of three programmable delay components, gate delay, RC delay and a rise/fall delay. The delay synthesizer circuit emulates the critical-path delay within 4% voltage accuracy over the full range of process deviation and voltage. This accurate tracking ability realizes the supply voltage scaling according to the fluctuation of the LSI's characteristic caused by the temperature and process deviation. The DVFM contributes not only the dynamic power reduction, but also the leakage power reduction. This microprocessor, fabricated in 0.18 μm CMOS embedded DRAM technology achieves 82% power reduction in a Personal Information Management scheduler (PIM) application and 40% power reduction in a MPEG4 movie playback application. As process technology shrinks, the DVFM scheme with leakage power compensation effect will become more important realizing in high-performance and low-power mobile consumer applications.

Kazuo Kumano

Papers

Dynamic Voltage and Frequency Management for a Low-Power Embedded Microprocessor