Showing papers by "Alberto Sangiovanni-Vincentelli published in 1987"

MIS: A Multiple-Level Logic Optimization System

Abstract: MIS is both an interactive and a batch-oriented multilevel logic synthesis and minimization system. MIS starts from the combinational logic extracted, typically, from a high-level description of a macrocell. It produces a multilevel set of optimized logic equations preserving the input-output behavior. The system includes both fast and slower (but more optimal) versions of algorithms for minimizing the area, and global timing optimization algorithms to meet system-level timing constraints. This paper provides an overview of the system and a description of the algorithms used. Included are some examples illustrating an input language used for specifying logic and don't-cares. Parts on an industrial chip have been re-synthesized using MIS with favorable results as compared to equivalent manual designs.

Multiple-Valued Minimization for PLA Optimization

Abstract: This paper describes both a heuristic algorithm, Espresso-MV, and an exact algorithm, Espresso-EXACT, for minimization of multiple-valued input, binary-valued output logic functions. Minimization of these functions is an important step in the optimization of programmable logic arrays (PLA's). In particular, the problems of two-level multiple-output minimization, minimization of PLA's with input decoders and solutions to the input encoding problem rely on efficient solutions to the multiple-valued minimization problem. Results are presented for a large class of PLA's taken from actual chip designs. These results show that the heuristic algorithm Espresso-MV comes very close to producing optimum solutions for most of the examples. Also, results from a chip design in progress at Berkeley show how important multiple-valued minimization can be for PLA optimization.

A Parallel Simulated Annealing Algorithm for the Placement of Macro-Cells

Abstract: A modification of the classical Simulated Annealing algorithm for the macro-cell placement problem is proposed for implementation on multiprocessor systems. The algorithm has been implemented on the Sequent Balance 8000, a multiprocessor system with a shared-memory architecture. Experimental results show that the new algorithm obtains results comparable in quality to those of the single processor version; processor utilization is greater than 80 percent using up to eight processors.

A Detailed Router Based on Incremental Routing Modifications: Mighty

Abstract: For the macrocell design style and for routing problems in which the routing regions are irregular, two-dimensional routers are often necessary. In this paper, a new routing technique that can be applied for general two-layer detailed routing problems, including switchboxes, channels, and partially routed areas, is presented. The routing regions that can be handled are very general: the boundaries can be described by any rectilinear edges, the pins can be on or inside the boundaries of the region, and the obstructions can be of any shape and size. The technique is based on an algorithm that routes the nets in the routing region incrementally and intelligently, and allows modifications and rip-up of nets when an existing shortest path is "far" from optimal or when no path exists. The modification steps (also called weak modification) relocate some segments of nets already routed to find a shorter path or to make room for a blocked net. The rip-up and reroute steps (called strong modifiction) remove segments of nets already routed to make room for a blocked connection; these steps are invoked only if weak modification fails. The algorithm has been rigorously proven to complete in finite time and its complexity has been analyzed. The algorithm has been implemented in the "C" programming language. Many test cases have been run, and on all the examples known in the literature the router has performed as well as or better than existing algorithms. In particular, Burstein's difficult switchbox example has been routed using one less column than the original data. In addition, the router has routed difficult channels such as Deutsch's in density and has performed better than or as well as YACR-II on all the channels available to us.

Logic Verification Algorithms and their Parallel Implementation

Abstract: LOVER incorporates a novel approach to combinational logic verification and obtains good results when compared to existing techniques. In this paper we describe a new verification algorithm, LOVER-PODEM, whose enumeration phase is based on PODEM. A variant of LOVER-PODEM, called PLOVER, is presented. We have developed, for the first time, parallel logic verification schemes. Issues in efficiently parallelizing both general and specific LOVER-based approaches to logic verification over a large number of processors are addressed. We discuss parallelism inherent in the LOVER framework regardless of what enumeration and simulation algorithms are used. Since the enumeration phase is the efficiency bottleneck in parallelizing LOVER-based approaches, we have developed parallel versions of PODEM-based enumeration algorithms. Experimental results are presented to show that high processor utilization can be achieved when these parallelisms are exploited. Speed-up factors of over 7.8 have been achieved with 8 processor configurations.

Design systems for VLSI circuits : logic synthesis and silicon compilation

Abstract: Introduction: Synthesis of LSI Circuits.- I: Synthesis Methods.- Procedural Design and Module Generation.- Module Generators for VLSI Design.- Abstraction and Layering in Silicon Compilation Tools.- Symbolic Layout and Procedural Design.- Physical Synthesis.- Automatic Layout of Integrated Circuits.- Logic Synthesis.- Algorithms for Multi-Level Logic Synthesis and Optimization.- Verification Algorithms for VLSI Synthesis.- Logic Synthesis.- Synthesis of Control Systems.- Towards Intelligent Silicon Compilation.- II. Synthesis Systems.- A Mixed-Media Approach to Module Generator Design.- Design of Module Generators and Silicon Compilers.- Layout Compilation.- The Socrates Logic Synthesis and Optimization System.- The Syco Silicon Compiler and Its Environment.- The MEGA System for Semi-Custom Design.- III. Synthesis Systems for Digital Signal Processing.- Automatic Generation of Digital Signal Processing Circuits.- Cathedral II: A Synthesis and Module Generation System for Multiprocessor Systems on a Chip.

Circuit Simulation on the Connection Machine

Abstract: Accurate circuit simulation is a very important step in the design of high performance integrated circuits. The ever increasing size of integrated circuits requires the use of an inordinate amount of computer time to be spent in circuit simulation. Parallel processors have been considered to speed up the simulation process. Massively parallel computers have been made available recently and present a new interesting paradigm for expensive CAD applications. This paper describes algorithms and programming techniques needed to develop SUM (Simulation Using Massively parallel computers), a relaxation-based circuit simulator on the Connection Machine, a massively parallel processor with up to 65536 processors. SUM can simulate circuits at almost constant CPU time per iteration, regardless of circuit size. SUM can simulate very large circuits. Circuit simulators running on the largest super computers can run circuits of comparable size, however SUM is easily scalable as the number of processors in the Connection Machine increases, with almost no increase in CPU time.

CAD tools for ASIC design

Abstract: Computer aids have been used for both the design and verification of electronic systems for many years. The recent explosion in the complexity of electronic systems that the advent of Very Large Scale Integration (VLSI) has allowed, has made the use of sophisticated computer-aided design tools indispensable. Computer aids will soon also provide key proprietary advantages as semiconductor and system design houses vie for the promising Application-Specific IC (ASIC) market of the next decade. This paper focusses on the techniques critical to both custom and ASIC design, the directions of present research and development for these areas, and future trends. In particular, recent developments in tools for the automated design of combinational logic are reviewed. These techniques include both algorithmic and rule-based approaches.

The Berkeley synthesis project

Abstract: A concentrated effort is being made to integrate the various synthesis tools available in our depart merit into a cohesive automated design environment. We report on our recent efforts and results with particular emphasis m the areas of module generation, circuit synthesis, and layout compaction.