A scan-based BIST scheme is presented which guarantees complete fault coverage with very low hardware overhead. A probabilistic analysis shows that the output of an LFSR which feeds a scan path has to be modified only at a few bits in order to transform the random patterns into a complete test set. These modifications may be implemented by a bit-flipping function which has the LFSR-state as an input, and flips the value shifted into the scan path at certain times. A procedure is described for synthesizing the additional bit-flipping circuitry, and the experimental results indicate that this mixed-mode BIST scheme requires less hardware for complete fault coverage than all the other scan-based BIST approaches published so far.

Bit-flipping BIST

We present the application of a deterministic logic BIST scheme on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for industrial circuits up to 100 K gates with 10000 test patterns, at a total area cost for BIST hardware of typically 5%-15%. It is demonstrated that a tradeoff is possible between test quality, test time, and silicon area. In contrast to BIST schemes based on test point insertion no modifications of the circuit under test are required, complete fault efficiency is guaranteed, and the impact on the design process is minimized.

/pdf/application-of-deterministic-logic-bist-on-industrial-43c4m51guf.pdf

Application of deterministic logic BIST on industrial circuits

This paper presents a new test resource partitioning scheme that is a hybrid approach between external testing and BIST. It reduces tester storage requirements and tester bandwidth requirements by orders of magnitude compared to conventional external testing, but requires much less area overhead than a full BIST implementation providing the same fault coverage. The proposed approach is based on weighted pseudo-random testing and uses a novel approach for compressing and storing the weight sets. Three levels of compression are used to greatly reduce test costs. No test points or any modifications are made to the function logic. The proposed scheme requires adding only a small amount of additional hardware to the STUMPS architecture. Experimental results comparing the proposed approach with other approaches are presented.

/pdf/hybrid-bist-based-on-weighted-pseudo-random-testing-a-new-25w369b89m.pdf

Hybrid BIST based on weighted pseudo-random testing: a new test resource partitioning scheme

A deterministic BIST scheme for circuits with multiple scan paths is presented. A procedure is described for synthesizing a pattern generator which stimulates all scan chains simultaneously and guarantees complete fault coverage. The new scheme may require less chip area than a classical LFSR-based approach while better or even complete fault coverage is obtained at the same time.

Deterministic BIST with multiple scan chains

In the past, Cellular Automata based models and machines [1] have been proposed for simulation of physical systems without any analytical insight into the behaviour of the underlying simulation machine. This paper makes a significant departure from this traditional approach. An elegant mathematical model using simple matrix algebra is reported in this paper for characterizing the behaviour of two-dimensional nearest neighbourhood linear cellular automata with null and periodic boundary conditions. Based on this mathematical model, a VLSI architecture of a Cellular Automata Machine (CAM) has been proposed. Interesting applications of CAM in the fields of image analysis and fractal image generation are also reported.

VLSI architecture of a cellular automata machine

In self-testable circuits, additional hardware is incorporated for generating test patterns and evaluating test responses. A built-off test strategy is presented which moves the additional hardware to a programmable extra chip. This is a low-cost test strategy in three ways: (1) the use of random patterns eliminates the expensive test-pattern computation; (2) a microcomputer and an ASIC (application-specific IC) replace the expensive automatic test equipment; and (3) the design for testability overhead is minimized. The presented ASIC generates random patterns, applies them to a circuit under test, and evaluates the test responses by signature analysis. It contains a hardware structure that can produce weighted random patterns corresponding to multiple programmable distributions. These patterns give a high fault coverage and allow short test lengths. A wide range of circuits can be tested as the only requirement is a scan path and no other test structures have to be built in. >

/pdf/testchip-a-chip-for-weighted-random-pattern-generation-rp3ol15ypx.pdf

TESTCHIP: a chip for weighted random pattern generation, evaluation, and test control

A chip is presented that generates weighted random patterns, applies them to a circuit under test and evaluates the test responses. The generated test patterns correspond to multiple sets of weights. Test response evaluation is done by signature analysis. The chip can easily be connected to a micro computer and thus constitutes the key element of a low-cost test equipment.

Albrecht P. Ströle

Papers

TESTCHIP: a chip for weighted random pattern generation, evaluation, and test control

TESTCHIP: A Chip for Weighted Random Pattern Generation, Evaluation, and Test Control