Showing papers in "IEEE Journal of Solid-state Circuits in 1991"

Two novel fully complementary self-biased CMOS differential amplifiers

Abstract: Two CMOS differential amplifiers, one that is intended for applications in which the input common-mode range is relatively limited, the complementary self-biased differential amplifier (CSDA), and one that is intended for applications in which the input common-mode range is bounded only by the supply voltages, the very-wide-common-mode-range differential amplifier (VCDA), are discussed. Both differ from conventional CMOS differential amplifiers in having fully complementary configurations and in being self-biased through negative feedback. The amplifiers have been applied as precision high-speed comparators in commercial VLSI CMOS integrated circuits. >

Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM's

Abstract: The speed of VLSI chips is increasingly limited by signal delay in long interconnect lines. A simple analysis shows that major speed improvements are possible when using current-mode rather than conventional voltage-mode signal transporting techniques. The key to this approach is the use of low-resistance current-signal circuits to drastically reduce the impedance level and the voltage swings on long interconnect lines. As an example, a simple four-transistor current-sense amplifier for fast CMOS SRAMs is proposed. The circuit presents a virtual short circuit to the bit lines, thus reducing the sensing delay, which is rendered practically insensitive to the bit-line capacitance. In addition, the virtual short circuit ensures equal bit-line voltages, thus eliminating the need for bit-line equalization during a read access. >

KOAN/ANAGRAM II: new tools for device-level analog placement and routing

Abstract: The authors describe KOAN and ANAGRAM II, new tools for device-level analog placement and routing. Analog layout tools that merely apply known digital macrocell techniques fall short of achieving the density and performance of handcrafted analog cells. KOAN and ANAGRAM II differ from previous approaches by using general algorithmic techniques to find critical device-level layout optimizations rather than relying on a large library of fixed-topology module generators. New placement algorithms implemented in KOAN handle complex layout symmetries, dynamic merging and abutment of individual devices, and flexible generation of wells and bulk constants. New routing algorithms implemented in ANAGRAM II handle arbitrary gridless design rules in addition to over-the-device, crosstalk-avoiding, mirror-symmetric, and self-symmetric wiring. Examples of CMOS and BiCMOS analog cell layouts produced by these tools are presented. >

Flexibility of interconnection structures for field-programmable gate arrays

Abstract: The relationship between the routability of a field-programmable gate array (FPGA) and the flexibility of its interconnection structures is examined. The flexibility of an FPGA is determined by the number and distribution of switches used in the interconnection. While good routability can be obtained with a high flexibility, a large number of switches will result in poor performance and logical density because each switch has significant delay and area. The minimum number of switches required to achieve good routability is determined by implementing several industrial circuits in a variety of interconnection architectures. These experiments indicate that high flexibility is essential for the connection block that joins the logic blocks to the routing channel, but a relative low flexibility is sufficient for switch blocks at the junction of horizontal and vertical channels. Furthermore, it is necessary to use only a few more routing tracks than the absolute minimum possible with structures of surprisingly low flexibility. >

A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3- mu m CMOS

Abstract: Described is a self-calibrated pipelined A/D converter technique potentially appropriate for such high-resolution video applications. This approach requires much less area than multistep flash approaches and requires fewer clock cycles than error averaging techniques. Since self-calibration can be performed during interframe intervals, this approach is particularly attractive for video applications. A 3- mu m CMOS prototype fabricated using this architecture achieves 13-b resolution at 2.5 Msample/s. consumes 100 mW, and occupies 40 kmil/sup 2/ (26 mm/sup 2/), with a single 5-V supply and two-phase nonoverlapping clock. >

Delay analysis of series-connected MOSFET circuits

Abstract: In order to derive analytical delay expressions for CMOS gates in the submicrometer region, a realistic MOS model which incorporates an nth power law MOS model is developed. Closed-form delay formulas are obtained for CMOS inverters and series-connected MOSFET structures (SCMSs) that include short-channel effects. It is shown that the ratio of the delay of NAND/NOR to the delay of the inverter becomes smaller in the submicrometer region, because the V/sub DS/ and V/sub GS/ of each MOSFET in the SCMS are smaller than those of an inverter MOSFET. The smaller voltages in turn mitigate and relax the severe carrier velocity saturation in miniaturized MOSFETs. The results of the analysis for submicrometer VLSI designs show that if the maximum number of series-connected MOSFETs is considered to be five in 2- mu m designs, then the number can be increased to six or seven in the submicrometer circuit design. In typical cases in VLSI designs, the delay ratio for N-SCMS is much less than N/sup 2/. The delay dependence on input terminal position for SCMS structures is also described. >

Generalized translinear circuit principle

Abstract: It is shown that a generalized interpretation of the translinear (TL) principle leads quite naturally to an extension to MOS circuits. It is shown that two distinct classes of TL circuits exist, one suitable for bipolar and the other for MOS implementation. The MOS-translinear (MTL) circuit principle is derived and an initial classification of simple MTL circuits is proposed. Some examples are given of MTL circuits synthesizing nonlinear functions. >

An experimental 1.5-V 64-Mb DRAM

Abstract: Low-voltage circuit technologies for higher-density dynamic RAMs (DRAMs) and their application to an experimental 64-Mb DRAM with a 1.5-V internal operating voltage are presented. A complementary current sensing scheme is proposed to reduce data transmission delay. A speed improvement of 20 ns was achieved when utilizing a 1.5-V power supply. An accurate and speed-enhanced half-V/sub CC/ voltage generator with a current-mirror amplifier and tri-state buffer is proposed. With it, a response time reduction of about 1.5 decades was realized. A word-line driver with a charge-pump circuit was developed to achieve a high boost ratio. A ratio of about 1.8 was obtained from a power supply voltage as low as 1.0 V. A 1.28 mu m/sup 2/ crown-shaped stacked-capacitor (CROWN) cell was also made to ensure a sufficient storage charge and to minimize data-line interference noise. An experimental 1.5 V 64 Mb DRAM was designed and fabricated with these technologies and 0.3 mu m electron-beam lithography. A typical access time of 70 ns was obtained, and a further reduction of 50 ns is expected based on simulation results. Thus, a high-speed performance, comparable to that of 16-Mb DRAMs, can be achieved with a typical power dissipation of 44 mW, one tenth that of 16-Mb DRAMs. This indicates that a low-voltage battery operation is a promising target for future DRAMs. >

Simultaneous switching ground noise calculation for packaged CMOS devices

Abstract: Here, it is assumed that the internal switching current is small compared to the output driver switching current. In the past, it was assumed that simultaneous switching noise created by CMOS outputs was directly proportional to the number of outputs switching simultaneously. Recent studies indicate that CMOS circuits exhibit sublinear behavior (due to the negative feedback influence) of power/ground noise (or bounce) as a function of the number of outputs switching simultaneously. Detailed electrical models, equations, and a trial architecture for calculating the switching noise are included. The results are compared to SPICE simulations and conventional power/ground noise calculations. The behavior of simultaneous switching noise as a function of constant-voltage (CV) device scaling is explained for small-geometry CMOS output drivers. >

A high-speed clamped bit-line current-mode sense amplifier

Abstract: A clamped bit-line current-mode sense amplifier that maintains a low-impedance fixed potential on the bit lines is introduced. Using a general model for active-drive memory cells that include the two-transistor (2T) and three-transistor (3T) dynamic cells and the four-transistor/two-resistor (4T-2R) and six-transistor (6T) static cells, the new sense amplifier is shown to have a response speed that is insensitive to bit-line capacitance. This is achieved by relocating the large bit-line capacitance to a node within the sense amplifier that has only a minimal effect on the speed of the circuit. Bit-line clamping also minimizes inter-bit-line voltage noise coupling. >

Circuit and architecture trade-offs for high-speed multiplication

Abstract: VLSI implementations of high-performance parallel multipliers are discussed. Circuit building blocks required for partial-product reduction are analyzed and two schemes leading to highly regular layouts are proposed. The circuit implementations related to the first-scheme in three different BiCMOS technologies are discussed. The die size and performance for nominal design rule values are compared, and the trend in scaling the feature sizes is studied. A silicon implementation of a prototype slice of an IEEE double-precision floating point multiplier in a 0.8- mu m double-metal BiCMOS technology is presented. >

An area model for on-chip memories and its application

Abstract: An area model suitable for comparing data buffers of different organizations (e.g. caches versus register files) and arbitrary sizes is described. The area model considers the supplied bandwidth of a memory cell and includes such buffer overhead as control logic, driver logic and tag storage. The model gave less than 10% error when verified against real caches and register files. It is shown that, comparing caches and register files in terms of area for the same storage capacity, caches generally occupy more area per bit than register files for small caches because the overhead dominates the cache area at these sizes. For larger caches, the smaller storage cells in the cache provide a smaller total cache area per bit than the register set. Studying cache performance (traffic ratio) as a function of area, it is shown that, for small caches (less than the area occupied by 256 registers bits-r.b.e.-or 32 b), direct-mapped caches perform significantly better than four-way set-associative caches and, for caches of medium areas (between 256 r.b.e. and 4096 r.b.e.), both direct-mapped and set-associative caches perform better than fully associative caches. >

A 50-MHz multibit sigma-delta modulator for 12-b 2-MHz A/D conversion

Abstract: The authors examine the application of oversampling techniques to analog-to-digital conversion at rates exceeding 1 MHz. A cascaded multibit sigma-delta ( Sigma Delta ) modulator that substantially reduces the oversampling ratio required for 12-b conversion while avoiding stringent component matching requirements is introduced. Issues concerning the design and implementation of the modulator are presented. At a sampling rate of 50 MHz and an oversampling ratio of 24, an implementation of the modulator in a 1- mu m CMOS technology achieves a dynamic range of 74 dB at a Nyquist conversion rate of 2.1 MHz. The experimental modulator is a fully differential circuit that operates from a single 5-V power supply and does not require calibration or component trimming. >

A 1 Mb EEPROM with MONOS memory cell for semiconductor disk application

Abstract: A 1 Mb 5 V-only EEPROM (electrically erasable programmable ROM) with metal-oxide-nitride-oxide-semiconductor (MONOS) memory cells specifically designed for a semiconductor disk application is described. The memory has high endurance to write/erase cycles and a relatively low programming voltage of +or-9 V. These advantages result from the structure and the characteristics of the MONOS memory cell. A newly developed dual-gate-type MONOS memory cell has a small unit cell area of 18.4 mu m/sup 2/ with 1.2 mu m lithography, and the die size of the fabricated chip is 5.3 mm*6.3 mm. A new programming scheme called multiblock erase solved the problem of slow programming speed. A programming speed of up to 1.1 mu s/B equivalent (140 ms/chip) was obtained. >

An analog neural network processor with programmable topology

Abstract: The architecture, implementation, and applications of a special-purpose neural network processor are described. The chip performs over 2000 multiplications and additions simultaneously. Its data path is particularly suitable for the convolutional topologies that are typical in classification networks, but can also be configured for fully connected or feedback topologies. Resources can be multiplexed to permit implementation of networks with several hundreds of thousands of connections on a single chip. Computations are performed with 6 b accuracy for the weights and 3 b for the neuron states. Analog processing is used internally for reduced power dissipation and higher density, but all input/output is digital to simplify system integration. The practicality of the chip is demonstrated with an implementation of a neural network for optical character recognition. This network contains over 130000 connections and was evaluated in 1 ms. >

Design of a 15-MHz CMOS continuous-time filter with on-chip tuning

Abstract: A fifth-order CMOS continuous-time Bessel filter with a tunable 6- to 15-MHz cutoff frequency is described. This fully balanced transconductance-capacitor (G/sub m/-C) leapfrog filter achieves a dynamic range of 55 dB while dissipating 96 mW in a 5-V 0.9- mu m CMOS process. The author reviews the disk drive application and filtering requirements, and explains why the G/sub m/-C continuous-time filtering approach was used. The on-chip master-slave tuning system uses a voltage-controlled oscillator (VCO). Experimental results are presented. >

A 10-b 70-MS/s CMOS D/A converter

Abstract: A 10-b 70-MS/s CMOS D/A converter fabricated in a 1- mu m CMOS technology is described. An integral linearity error caused by error distributions of current sources is reduced by a new switching sequence called hierarchical symmetrical switching. A differential linearity error caused by an off-axis drain-source implantation is reduced by the layout technique of current sources. The D/A converter is fabricated by using a single-polycide double-metal standard digital process. Both the integral and the differential linearity errors are less than +or-0.5 LSB. The settling time to +or-0.1 % is less than 14 ns. The worst-case glitch energy is approximately 60 pV-s. This D/A converter has a single power supply of 5 V and dissipates 170 mW at 70 MS/s. The chip size is 2.02 mm*1.87 mm. >

A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture

Abstract: The authors describe a 512 K CMOS static RAM (SRAM) with emitter-coupled-logic (ECL) interfaces which has a 2-ns cycle time and a 3.8-ns access time, both of which are valid for random READ/WRITE operations. The CMOS technology and the physical organization of the chip are briefly discussed, and the pipelined architecture of the chip is described. Detailed measurements of internal chip waveforms demonstrating 2-ns cycle time operation are presented. The impact of wire RC delays on performance is discussed. Circuit examples that demonstrate the implementation of the pipelined architecture are included. Measurements of operating margins, access time, and cycle time are outlined. >

Optimum buffer circuits for driving long uniform lines

Abstract: The design of optimum buffer circuits for driving long uniform lines is discussed. Given a uniform line, the size of the buffer driving the line, and the value of the capacitive load driven by the line, the problem considered consists of determining the type, number, and position of buffers that minimize the delay in the line. A variation of this problem that is also considered consists of minimizing the delay in the line when the area occupied by the buffers is constrained; this leads to the solution of the problem of minimizing the delay in driving a pure capacitive load under buffer area constraint. The optimal solution is formally developed, and some very good approximate solutions that can be obtained via simple computations are presented. It is shown that accepting a small increase in delay (of usually 5% over the minimum) can lead to a significant (about 50%) decrease in the area occupied by the buffers. Design curves that allow the reader to determine the optimum buffers with little effort are presented. >

Switched-current circuit design issues

Abstract: Switched-current (SI) circuits represent a current-mode analog sampled-data signal processing technique realizable in standard digital CMOS technologies. Unlike switched-capacitor (SC) circuits, SI circuits require only a standard digital CMOS process. SI circuits use MOS transistors as the storage elements to provide analog memory capability. Similar to the operation of dynamic logic circuits, a voltage is sampled onto the gate of a MOSFET and held on its noncritical gate capacitance. The held voltage signal on the gate causes a corresponding held current signal in the drain, usually proportional to the square of the gate-to-source voltage. Design issues related to the implementation and performance of SI circuits are presented. SI filters show comparable performance to SC filters except in terms of passband accuracy. The major source of error is nonunity current gain in the SI integrator due to device mismatch and clock-feedthrough effects. For the initial CMOS prototypes, the current track and hold (T/H) gain error was about 2.5%. >

Realization of a 1-V active filter using a linearization technique employing plurality of emitter-coupled pairs

Abstract: A low voltage (1 V), low-power (100 mu W), and low-frequency (9 kHz) fifth-order fully integrated active low-pass filter (LPF) using a bipolar technology is described. Novel highly linear transconductors consisting of N emitter-coupled pairs were designed for low-voltage operation. The linear input range is expanded to about 100 mV/sub p-p/ at 1% error with N=4, which is about twice that of the conventional linearization technique. The filter is basically a gyrator-capacitor type, in which gyrators are implemented by using the linearized transconductors. Large time constants were realized with very low current (540 nA/transconductor) owing to the high transconductance-to-operating-current ratio of the linearized transconductors. Measured results show a passband ripple of 1.5 dB, a minimum stopband rejection of 70 dB, and a dynamic range of 56 dB, despite a very high nominal impedance (400 k Omega ). Practical limitations of this approach are also discussed, such as the sensitivity of the linearized transconductors against process variations, noise, and frequency limitations. >

An active resistor network for Gaussian filtering of images

Abstract: The architecture of an active resistive mesh containing both positive and negative resistors to implement a Gaussian convolution in two dimensions is described. With an embedded array of photoreceptors, this may be used for image detection and smoothing. The convolution width is continuously variable by 2:1 under user control. Analog circuits implement a 45*40 mesh on a 2- mu m CMOS integrated circuit, and perform an entire convolution in 20 mu s on applied images. >

A CMOS implementation of FitzHugh-Nagumo neuron model

Abstract: A CMOS circuit that emulates the FitzHugh-Nagumo neuron model is introduced. A complete derivation of the neuron model is presented, starting with the description of the fundamental biological mechanisms involved in the living neural cell, followed by the mathematical model formulation extracted from these mechanisms. A circuit theory technique for obtaining a physical IC suitable circuit that emulates the derived mathematical equations is then presented, culminating with the presentation of experimental results on a chip fabricated in a 2- mu m double-metal, double-poly CMOS process. It is emphasized that the FitzHugh-Nagumo model is very adequate for emulation of small biological systems. A reduced-complexity oscillatory model suitable for implementation of relatively large neural network architectures is also introduced with several corresponding CMOS realizations and measured results. >

A CMOS four-quadrant analog multiplier with single-ended voltage output and improved temperature performance

Abstract: An all-MOS, four-quadrant analog multiplier with single-ended voltage output and good temperature performance is presented. It is based on a linear MOS transconductor with extended operation range to four quadrants and on a linear MOS resistor. The temperature behavior of the multiplier is improved by a factor of 10. The multiplier was realized using a 3- mu m p-well self-aligned contact CMOS (SACMOS) process. A linearity better than 1% for each of the input voltages of 5 V/sub p-p/, a bandwidth from DC to 1.2 MHz, and output noise 73 dB below full scale were achieved. The active chip area is 210 mil/sup 2/ and power consumption is 6 mW. A new approach for implementing a temperature-independent analog multiplier is proposed. >

Microfabricated thermal absolute-pressure sensor with on-chip digital front-end processor

Abstract: A thermal absolute pressure sensor of the heated microbridge type has been integrated with an active bias circuit and an 8-b successive approximation register analog/digital (A/D) converter. The chip, which contains about 1000 devices, is sensitive to variations in absolute gas pressure between 10 and 10/sup 4/ Pa, and it is implemented in a 4-Um NMOS technology merged with the microsensor process. The output of the chip is a robust digital signal adequate for transmission in high noise environments. >

Integrated sensor and range-finding analog signal processor

Abstract: The authors present experimental results from an array of cells, each of which contains a photodiode and the analog signal-processing circuitry needed for light-stripe range finding. Prototype circuits were fabricated through MOSIS in a 2- mu m CMOS p-well double-metal, double-poly process. This design builds on some of the ideas that have been developed for ICs that integrate signal-processing circuitry with photosensors. In the case of light-stripe range finding, the increase in cell complexity from sensing only to sensing and processing makes the modification of the operational principle of range finding practical, which in turn results in a dramatic improvement in performance. The IC array of photosensor and analog signal processor cells that acquires 1000 frames of light-stripe range data per second-two orders of magnitude faster than conventional light-stripe range-finding methods. The highly parallel range-finding algorithm used requires that the output of each photosensor site be continuously monitored. Prototype high-speed range-finding systems have been built using a 5*5 array and a 28*32 array of these sensing elements. >

Second-order sigma-delta modulation for digital-audio signal acquisition

Abstract: The authors compare the second-order sigma-delta ( Sigma Delta ) modulator to several alternative modulator architectures in the context of digital-audio signal acquisition. Design details and experimental results are presented for a 1 mu m CMOS implementation that does not require error correction or component trimming to achieve virtually ideal 16 b performance at a conversion rate of 50 kHz. The experimental modulator is a fully differential circuit that operates from a single 5 V power supply and does not require the use of precision sample-and-hold circuitry. With an oversampling ratio of 256 and a clock rate of 12.8 MHz, the modulator achieves a 98 dB dynamic range and a peak signal-to-(noise+distortion) ratio (SNDR) of 94 dB. Measurements and simulations of discrete noise peaks in the output spectrum that result from limit-cycle oscillations are also presented and discussed. >

A high-speed sample-and-hold technique using a Miller hold capacitance

Abstract: A circuit technique is introduced for increasing the precision of an open-loop sample-and-hold circuit without significantly reducing the sampling speed. With this technique, the sampling error resulting from input-dependent charge injection of the sampling switch is significantly attenuated by sampling the input voltage onto a capacitance that is small during the sample mode but is, in effect, increased during the transition to the hold mode through the action of Miller feedback. The technique thus allows for a high sampling speed without the precision penalty traditionally associated with open-loop sample-and-hold circuits. A sample-and-hold circuit based on the proposed approach has been designed and fabricated in a 1- mu m CMOS technology, and an order-of-magnitude of reduction in the input-dependent charge injection has been demonstrated experimentally. This prototype circuit is capable of sampling an input to a precision of 8 b with an acquisition time of 5 ns. The experimental sample-and-hold circuit operates from a single 5-V supply and dissipates 26.5 mW. >

A 10 ns 54*54 b parallel structured full array multiplier with 0.5 mu m CMOS technology

Abstract: A 54 b*54 b multiplier fabricated in a double-metal 0.5 mu m CMOS technology is described. The 54 b*54 b full array is adopted to complete multiplication within one latency. A 10 ns multiplication time is achieved by optimizing both the propagation time of the part consisting of 4-2 compressors and the propagation time of the final adder part. The n-channel pass-transistor circuit and the p-channel load circuit are used at the critical blocks to improve the multiplication speed. This multiplier is intended to be applied to double-precision floating-point data processing based on the IEEE standard up to clock range of 100 MHz. >

Double-edge-triggered D-flip-flops for high-speed CMOS circuits

Abstract: Two circuits are proposed for double edge-triggered D flip-flops (DETDFFs). A DETDFF responds to both edges of the clock pulse. As compared with positive or negative edge-triggered flip-flops, a DETDFF has advantages in terms of power dissipation and speed. Delay figures for these circuits are measured by simulation. It is shown that these circuits are faster and have lower transistor counts than previously reported circuits. It is shown that these flip-flops can be used at 320-400-MHz clock frequency in a 2- mu m technology. >