IEt:E.
JOU
R
NAL
OF
SQlIl)
·ST
ATE
CI
RCUITS
. VOL
26
.
NO
.
7.
JULY
1
99
1
TESTCHIP: A Chip for Weighted Random
Pattern Generation, Evaluation,
and Test Control
Albrec
ht P. S
tr
ole and Hans·J
oach
im
Wund
erlich, Associate Member , IEEE
Abstrac
l
~
ln
s
elf
.les
table
cin:uil
S
ad
ditional
hardwa
re
is in·
corporated
for ge
neratin
g
tf
st
pattern
s a
nd
eva
luating
I
ts
t
reo
sponses. In this
pa~r
a built
·o
lT
test ,
Irate
gy
is prese
nl
ed which
mo
'es
the a
ddition
al
hllrdwarf
to a
programm
able
extra
chip.
Thi
s is
II
l
ow-<:ust
test strategy in Ih
rH
..
'ays: " the use
or
random
patt
e
rn
s
eliminale
s Ihe expens
i"
e lest
patt
em
computa
·
tion; 2) a microcom
puter
~
od
an
ASIC
I"f
pl
act
Ihe
e.~pe
n
s
ln
au
tom
atic
lest
equipmenl
;
and
3)
th
e dn ign
fu
r tes
tabilit
y
o~erheads
An>
minim
b:ed.
The
pre
se
ot
ed ASIC g
en
erlltes
ran
·
dom
plIltem
s,
applies
th
em tu a
ciR"
uit
under
lest, a
nd
e.'atuAtes
th
e test
n>
sponses by sig
nature
ana
lysis.
II
co
ntain
s a
hard
....
are
S
lru
c
tu
n>
Ih
al
Can
produce
_ighled
random
pallern
s corn>·
spclndinll
10
mullipl
e
programmabte
dis
lr
ibulions. These
pal
·
le
rns
gh·e
II
hi
gh r
aul
t
co
.·erage
and
allow sh
ort
test le
ngth
s. A
wide
ra
nge
of
ciR"uilS
ca
n lie tesl
ed
as
the
only l't<Iuirement is
II
sca
n pa
lh
and
no
other
les. struCIun>S
ha.
·e 10 Ix-
buill
in.
Index
Ttn
ll.\"~
Built
-0
1T
les
t,
low·cosl lest, multiple ... eiltht
,.
randum
It
sl, lest etjuipnlenl.
I.
INTRODU('TION
C
ONVEN
TI
ONAL lest stratt:gies
u5ing
dl:1erministk
test pattern generation and automatic test equip·
ment cause high costs and lead to severe problems, parti
e'
ularly
fo
r
AS
I
C's
with moderate production
volu
mes.
As
an
alternative, random pattern testing
is
altraetive,
si
n
ce
the computationally imensive automatic test pattern gen·
eration
is
eliminatcd and pseudorandom pattern genera-
tors can
be
bui
lt
with a small amount
of
hardware.
Th
e basic
te~t
configuration
is
shown
in
Fig.
I.
A
pattern generator
(
PO
) produces bit patterns that arc
applied to the primary inputs
of
the circuit under test
(CUT). The responses at the primary outputs of the CUT
are
fed
to a test
responSC
compressor (TR
C).
c.g., a
signature register. A cOntrol unit clocks the PO and the
TRC
and
COntrols
the CUT (reset, clock. etc.).
When sequential
ci
rcuits are 1ested using this basic
<'"Onfigurat
ion, the test length
may
become very large,
since a random pattern sequence to
ta
ke the CUT to a
Manu
sc
ri
pl
received December 3. 1
990;
revi
se
d Mareh
8.
1
991.
A. P. Slrol( is "'ilh
lh
e In>tilule of Compuler
D.
;i,
n a
nd
Fa
ull
Tolera
nce
. Univcn;cy of Karlsruhe,
1)
.7500 Ka
tl"uh
c I. German
y.
H.·J. Wunderlich is "'ilh lhe Uni...,rsily of I)uisburg. Duisbur
g,
G~r.
man
y. on
Ic
a
w:
from
lh
e iMlilUle of Compuler Design a
nd
Faull
Tolerance, Uni"c
rs
il
Y of Ka
rl
sruhc.
0·
7500 Ka
rl
sruhe I.
(krm
an
y.
IEEE
Log
Number 91
(XX)4
2.
B
-'
-
._.
-,
,
,
,
Fi
g.
1.
Ra
sic
le
<l
C4)nfi
guralion.
;;--
~--::i--~~--
;~---
L
:
C::;
~
I
~
'::J
B
:L
--
:;-;
-
«lII1rOI
:::'''--
''
-'
--
E
.....
_1
~
:
--,1;;'"...1
: l ,
,,-.,-
,
~
....
-
.....
-
Fi
, .
2.
Tesc
co
nfi,ural
io
n
for
a sequential CUT.
given state can increase at a greater than
e~poncnt
ial
rate
with the number
of
nip·flops of the CUT
[19
). In order to
avoid this, sequential
ci
rcuits arc usua
ll
y prov
id
ed with a
scan path.
In the test mode the
ci
rcuit
is
partitioned into
a combinational logic part and a set of storage elements
configured a shift register chain. The test configuration
must be modified (
Fi
g.
2)
since additional
pattern~
are
lo
aded
se
ri
ll
ll
y into the sean path, :Ind the output
of
the
scan path
is
eval
uated. too.
The tasks
of
pattern generation,
respon~
comp
r
cs-~
i
on
,
and
te
st control can be performed
by
automatic test
equipment. which must
be ahle to apply a large
se
t
of
test
patterns
at
high
speed. High·speed testing is required for
economical reasons
in
order to shonen the test time, and
for technical reasons
in
order to obtain a certain product
quality as
some fau
lt
s arc
not
detectable otherwise. Usu·
ally the test patterns are precomputed and stored
in
a fast
buffer.
Empirical s
lu
dies have shown that !he size
of
determin-
istic test sets increases
in
the order
of
the
ci
rcu
it
complex-
ity.
but since a pallern is shi
ft
ed into the scan path
serially the testing time
grov.'S
quadratically
[71.
Moreover.
OO
I
H·
9200
j9
1j 0
700-
1056S01.00 "
1991
IEE
E
STROLE
AND
WUNDERUCIL
CIIII'
FOR
WEIGHTED
RANI)O~1
I'Al-I'ER:>l G ENER,
\T!ON
"'"
these large test
~clS
cannot entirely
be
stored
in
the
buffer; they
mUM
be
divi
ded into sever
al
blocks and
downloaded from some backup storage. Downloading
re-
quires a time which exceeds the duration
of
applying
th
e
patterns
10
the CUT
by
orders
of
ma
gnitude.
If
randomly
chosen bit
pallems are applied
10
the inputs
of
the circuit
und
er
test, they can easily
be
generated on-line during the
test execution, and only a small amount of data
is
re-
quired to define the entire test.
In
[15J
deterministic tests and random pattern tests arc
compared. Empirical results on a large number
of
LSSD
logic chips
of
varying size
give
a rangc of about
10
to
50
limes more weighted random pallerns than deterministic
patterns. But the
la
rger number
of
random patterns can
be applied
by
external test equipment
in
less time than a
deterministic set,
as
no
downloading
is
required.
In
addi-
tion, Ihe
inc
rease
in
the number
of
pallerns (test length)
improves the ability
to
detect nonmodeled faults (e.g
..
shorts, delay and transition
fa
ults).
The
automatic test equipment can
be
avoided if the
PO
'
s,
the
TRC
, and the test control unit are implemented
on the chip itself
(built-in self-test)
or
moved to an extra
chip (built-off
test). An
ex
tra chip
is
of len more advanta-
geous, as Ihe design effort and the silicon arca
for
II
built-in self-test are saved. Except for a scan path, no
other test features nced to
be intcgralcd into the
CUT_
Such
an
approach for extcrn
al
random pattern gcnera-
tion was reported
in
(I] and
[61.
A higher fault coverage
is
allainable
if
weighted
pat1ern~
are used
\181.
In
[15J
a
complex system
for
wcightcd random pattcrn testing
is
described for the production test of
LSSD
logic chips at
IBM.
In this paper a
si
ngl
e chip for a built-ofr test
is
presented that
ge
nerates weighted random paflcrns cor-
rCSJXlnding
to multiple dist ributions, performs sigmlture
analysis, ,md controls
th
e whole process.
The
central
paramcters are programmable
in
o
rd
er
to adapt them to a
wide
fllnge of CUT's. This makes the designcd chip a
key
clement
in
building 10w·cost test equipment_ Curren
tl
y
the prcsented test system is intcndcd to be used for
testing chips
of
multiehip projects designed
by
stude
nt
s.
This paper is an extcnsion
of
1131.
Seclion J 1 describes
the characteristic features of a random pattern test using
multiple distributions
and its advantages for a built·off
test_
In
Section III
,I
weighted random pallern gcnerator
ili
presented thai can Ix: programmed for multiple distri-
butions. The test eonfiguralion and Ihe chip design are
described
in
Section IV. Section V demonstrates the
application
of
the chip. Finally, Scction VI concludes with
a short summary.
II.
R
A
.
\lr)()~
PA1
-
'H
tN
TEST
CORRI'
_
'II'ON
DING
TO
M U
l.TlPl.£
D'
S
TR'U
U1"IONS
Deterministic tcst pllltems afe computed
in
ord
er
to
detect the faults
of
a certain fault model. A lest pallern
for a fault must result
in
a response at the primary
outputs that differs from the fault-free case. This
way
of
test generation requires a large amount
of
computation.
the deterministic test
~et
mu
st be stored, and complex
equipment
is
needed to execule the
te
st at a sufficiently
high speed.
A random test dispenses with the time-con-
su
ming test pattern computation.
In the following only combinational circuits and sc·
quential circuits with a com
pl
ete scan path arc consid-
ered. The eXlension to more general sequential
ci
rcuits
can
be
found
in
[19J.
Let
J,
~
(i
l
,'
.
-,
i
~l
be the primary
inputs
of
a circuit
S,
a
nd
let F be the set of faulls of
S.
A
tuple
B
'-
(bl
....
,b.)
of
Boolean random variables is as-
signed to Ihe primary inputs I. A Boolean random vari-
able b
,
gets the value
ONE
wilh probability
Xi
,.
PCb,)
e
[0,
I]
and tbe value
~F.:RO
with probability 1-
x,_
The
Boolean rllndom variables b
"
-
·.b.
arc independent, if
'rJ)
c {J.
··
·,IIJ
"(f1
/"
lb
j ) - n , £
lX
, holds.
Th
e tuple X
,-
(Xl'···
' X. ) E [0, I
I"
of real numbers
(inplIl
probobili-
ties) uniquely determines the tuple
13
",.
(h
,
,··
·.b")
of
independent Boolean random variables and defines a
d
i
~tribulion
of the random patterns at the primary inputs.
The
v.llue
of
each node u
of
the
ci
rcuit
i~
a Boolean
function of the
valu~s
at the primary inputs.
So
the
prob;lbility that the node
v takes the value
ONE
(signal
IJTobobilily)
is
r..'omplclely
determined
by
the tuple X. Let
H/)
be the complete sct of pallerns that detects the fault
f. Then
f1lX)
,. P
(B
E
T(j)
is
the probability
th:1I
a
randomly chosen paltern B detects the fault f (fau
lt
detection probability). For an arbitrary tuple X where
0 < x, < I for i - I,
'"
,1/,
each nonredundant fault / E F
can be detected, hence all the detection probabilities
p,
().')
arc positive. For X - (0.5.'
_.
,0
.5) all input pat-
terns arc equally likely and
appeH
wi
th
prohability
1/2"
.
In
this case the fault detection probability is
P,
W.5,
_·
·,O
.
5)
- IT(j)1;2". If a fault has only
few
test
pallerns,
it
results
in
a very small detection probability.
The probability thai a fault /
is
detect
ed
by
at least onc
pattern
is
1-
(1
-
plX»"';
the expected detection
of
a
fault
in
a faulty circuit by a set
of
N input pall
ems
(fa
ult
cOL'tmge)
is
(sec
[IOJ)
<
I)
The
probability
P(N,
X)
that each fault f E F
is
detected
by
N random patterns
is
estimated
by
the formula
The
formula holds
ex
actly
if
it
is
assumed that
th
e delee-
tion
of
some faults by N patterns fonns completely inde-
pendent events.
But
even without this assumption
it
gives
a very precise estimation
1181-
Equations
(I)
and (2) show the interdependence be-
tween the test length N on the one side and the fault
coverage
and the probability
of
detecting
all
faults on the
other
side. Both PC(N,
X)
and peN,
X)
increase Slrietly
monotonically
with
the test lenglh
N.
In
order
to
obtain a
predetermined test
Quality
in
terms of certain
va
lu
es of
FClN,
X)
or
I'{N,
X),
the lest length chosen must be
''"'
sufficienlly large. Reference
(16]
gives an efficient proce-
dure
to
determine
the test length for a given value C < I
(confidenu)
of
the probability P(
N,
X)
.
Only the few faults F' c F with lowest
detec
ti
on proba-
bility
have
im
pact on the required test length. In the
worst case all fau
lt
s
of
F'
have the same minimal detec-
tion probability p(
X).
Then
(2) leads
to
I N( X
)-
n [ '
_(I
_
p(
X
)N
[
/
fii.
r
[
HI
"
- 1-
(I
-
p(X))
.
(3)
and the necessary number N
of
random patterns to reach
a given probability
P(
N ,
X)
'"
c,
C",
I, can
be
estimated
by
1
..
""
(,,
I '
-,
'1)
'-.-,,
'
,,"
,,
( I
_--=
C
:..c
)
N·
-
p
(X)
.
(4)
The lest length increases
li
nearly with the reciprocal
of
the minimal raul! delec
ti
on probability. As a conse-
quence, the t
es
t length for equally distributed input prob-
abilities
(X
- (O.5,···,O.S» may grow exponentially with
the number
of
the
primary
outpu
t
s.
To reduce the test length,
tw
o approaches arc known.
One
lIpproach modifics
th
e:
structure:
of
th
e CUT and
inse
rt
s additional gates and multiplexers
in
orde
r
10
im·
prove the controllability and obsew.lbility
of
c
ri
tical parts
of
Ihe
cm
(e.g ..
[51.I12D
. Bul Ihis docs not con
fo
rm
to
the intention
of
a built-o
ff
test. since
illead
s
10
a
dd
itional
hardware
COS
IS for Ihe
CUT
.
Th
e
other
approach is 10
modify the random
pll
llern
s.
By changing the input prob-
abilities X i' the detection prob
ab
ilities
of
the faults with
lo
we
st detection probabilities ca n
be
increased. This
re·
duces the test lenglh for :I given confidence correspond·
ing to (4).
The
input probabilities x,. also ca
ll
ed weight
s.
ar
e optimized such Ihal
the
fault coverage or
th
e
proba·
hility
of
detecting all faults reaches a specified
vlll
ue with
a minimum number of
...
..
eight
ed
random pall
erns
. This
can reduce test
lengths
by
ord
en
of
magnitudc. To test
the
IS
CAS'S5
benc
hmark circuit
c880.
for example, only
660 optimized random pllttcrns arc
rCQuired
TlI
th
cr
than
37000
patterns
wi
thout optimization
[4J,
[8].
Some circuits are resistant to this kind
of
optimiza
ti
on,
whcn only
onc
distribution (one tuple
of
wei
ghts) is used.
Improving the fault detection probabilitics
in
some
parts
of these drcuilS requires weights that change
th
e faul!
detection probabilties in
other
paris
f
or
th
e
....
·orse and
vicc
versa. Fig. 3 g
ive
s an example. When an allempt is
made
to
optimize the weights
fOT
t
hi
s circuit. the
AN
O
)2
favors weights n
ear
1.
and the o R32 favors weights n
car
O.
For the combination of an
/\N
oJ
2 and
lin
oR32. no
bC
ller
single tuple
of
weights exists than X - (0.5,· . ·,0.5). This
would require
II test length
of
N
'"
4.8.
10
111
10
get a
confidence
of
C
..
0.999.
Th
c problem is solved
by
first
applying 600 pallerns with input
pr
oba
bilities .r
l
" . . . -
x
ll
-
ll
/ff5
a
nd
then 600 patterns with input probabili·
ties
Xl:·
- Xn '"
l-
J
~
/ff5.
This way the confidence
C
..
0.999 is
ob
tain
cd
with N
..
1200 random patterns.
IEI:I: JOURNAL
OF
SOLJI)·STATE C
IR
CUITS.
I,IO
I
~
26.
1'0.
7.
JU
L.Y 1
9')1
•
I--
""""
"
I--
~"
F
i~
.
J. Circuil
Ih~L
b
rool
random le$la
bt
e
u,;nl
one dislribulion.
Multip
le
tuples
of
wcights X I •
..
' . X ·
can
shorten the
test length in all cases.
Th
en
the probability "
(N
, X ) to
detect all faults
of
f' is given by
,
N
.-
r.
N,.
,.
,
(5)
H
ere
a number k. k tupl
eso
fwcight
s
X
"-
(x
:
,
···
,x~),
and k numbers
N"
i
..
I.
···,
k, must be found such that
I'(
N,
X)
exceeds a given confidence value C and N is
minima
l.
The test configuration
pr
ese
nt
ed
in
th
e foliow·
ing sections uscs weighted random
pattern
s correspond·
ing to multiple distribu
ti
ons.
Methods
to
optimize the weights for a given CUT lire
reported
in
IlOj,
[II).
[1
5J.
[1
61.
and [18J. Probabilistic
testability analysis provides m
eans
to
devel
op
an
ob
jective
function for the optimization procedure. A
f
auh<ove
rage
estimate based on controllability and observability mea-
sures
or
the probability that a
ll
faults
aTe
detected
can
be
used. Formula (2)
is
tr
ansformed into
In(l
....
(X
)).
- L
(l
- P/
(X
)(
",
- L e
NP
J
(XI
/_
J. / C J
(6)
using some well·known approximations. A tuple X E
[0.
If
is ca
ll
ed opt imal. if the objec
ti
ve function
Ii
~
(
X)
''"'
L e
-N
P
,,"
X)
/ @F
(7)
is minimum.
Ob
vious
ly
this corresponds to the fact that
the probability of detecting all faults
by
N patterns is
maximum.
Th
e objec
ti
ve function (7) is strictly oon
vex
with respect to a singlc variable.
Th
e first partial deriva·
ti
ve
of
(7)
can
be
co
mputed explici
tl
y, and the
opti
mal
value for
x,. resulting in il8,t
(X
)/ ilx, -
O.
can be found
by
the bisection method. Applying this procedure
to
the
variabh:s .r
I"
x 2
'·
..•
X
~
itera
ti
vely, an optimal single tuple
X is deter
mi
ned.
For multiple dist
ri
butions the set of faults F is p
ar
ti
·
tioned into k subsets FI U F! U . . . U f
t
..
F, and for
each
subset fi an optimal tuple X' of weights
is
com·
puted. First, the set F
is
split into Iwosubscts
F.
U F
z
_ F.
STR61
_E
AI'D
WUNI)ERI.ICIl
:
CHIP
FOil.
WEIGHTED
I(I\NDOM
PAITEKl'I
GENERATION
,~,
E1_cIernenI
o oddi..".
®
......
Dp6cMion
1»'
r ,
Fig. 4. Line
..
feedback shih
regi~ler
in
modular
f()rm
.
such that
.s
,
O(Xl)
+
.s
.
~(X1)
:
_
L e-
N
I'/I
X ,1
J
..
f ',
+
r:
e-
NI'
}
IX
,
,<.s,,(X)
(8)
f E F,
is
minimum for optimal tuples X.
Xl.
and X 2. The
subsets
F,
and F
z
are constructed
by
enumerating the
faults;
a gradient optimization technique
is
used
to
decide
whether
10
take a
f<Jult
to
FI
or
to F
2
• This procedure is
iteratively applied
to
the subsets that require the largest
test sets. unlit the
leSI
length
is
sufficiently small.
Il
l.
RANDOM
PAlTERN
GE!'I:ERATION
A. Gellerarioll
of
Weiglued
P;K:udorandom
Pal/ems
The often used term '"random" pattern
is
somewhal
misleading
as
the patterns arc not truly
ra
ndom patterns
bul algorithmically generated
pseudoralldom patterns.
Pseudorandom pallerns arc reproducible. So the correct
reSponse of the circuit. the correct signature, and the
fault
coverage can be computcd
by
simulation. The for-
mulas of Section II, although developed for truly random
patterns,
give
precise estimations (or pseudorandom pat-
terns.
too, and the same optimization procedures can
bc
applied
[181.
Pseudorandom pattcrns never
inc
rease the
test length.
Equally distributed pseudorandom
patterns can
be
gen-
erated using a linear feedback shift register (LFSR) over
the field
Gf"(Z)
as shown
in
Fig.
4.
If the characteristic
polynomial
r(x)
- x' +rk _
lx·
-
I
+
...
+r
1
x + l,
r
iE
(O.
I)
for i -
I.
"
·.k
- I.
is
primitive. the state transition
diagram
of
the LFSR comprises a cycle
of
length
Zk_1
and a
cycle
of length I, i.c., the aU-zEllo state. When the
LFSR
is
started
in
a Slate differenl from the
all-ZERo
state,
it
produces bit sequences
of
period
Z*
- I at all its
slages. Thesc bit sequences are pseudorandom
sequences
a~
thcy have features
very
similar to truly random se-
quences
[8J
,
[20J.
ZERO
and
ONE
have almost the same
frequency. Within one period of length
Zk
- I there are
2'
1_
/
ZERO'S
and 2
k
-
1
ONE
'
S.
A sequence
of
i times a
ZE
RO
(ONE)
immediately followed
by
another
is
called a
ZERO
run
(Or-E
run) of length i. In Ihe produced bit
sequence.
I/Z'
of
the
ZERO
runs and I/ Z; of the
ONE
runs have the length i. Furthermore. the autocorrelation
is
as small as possible.
For
a weightcd random test. random bit sequences with
we
ights different from 0.5
are
required. To this Ilurpose
the bits
of
several independent random bit sequences
of
we
ight
0.5
arc combined
by
a Boolean function 1 (Fig. 5).
The
number
of
min
terms
of
the function 1 determines
"fi
: fllnaoon 0
,
'.
Fill
. 5. Generation
of.
weighted
r~ndom
bit
s.eqUCIICC.
t
he
probability
of
a
ONE
in
the output bit scquence. The
output
scquence
is
also a random scquenee.
For generating weights with a quantization
of
1/8,
the
following seven Boolean functions can be used:
fl
".
0ta~oJ
f
2=
a
Z
(Jl
fJ
~
01
+
ala
l
f. - a
J
f
s-
~
-
tJ,
+
ala]
16
-
!;
- a!tJJ
17
-
7.
"
01(J1
0
J'
As
each function
f"
I
'"'
I,'
.
',1,
has i minterms.
it
pro-
duces a pseudor
an
d
om
bit sequence
of
weight i
/8.
In recent years, several hardware structures have been
proposed th:.t generate weighted pseudorandom patterns
[3J,
[IIJ. [lSI,
117
1.
All
of
them are based on an LFSR with
a primitive feedback polynomial. The LFSR
is
tapped at
some stages and the pseudorandom bit streams at these
stages arc combined using Boolean funclions and
multi-
plexers
to
get the desired
weig
hts. The approaches differ
in
the selection
of
the tap positions and
in
the
way
the bit
streams are combined. But none
of
them allows pr
o--
grammable distributions integrated on a single chip.
8.
Tlte
Elft"C1
01
QU(Jlllizalio,r
The
computed optimized weights
x;
fo
r a given
CUT
arc real numbers out
of
[0,
J}.
As
only the subset
of
weights
is
used that can easily be implemented
by
Boo!can
functions as shown
in
Fig.
S,
the
reali~ed
input probabili-
ties differ from the computed values and the test length
is
influenced.
Let
X be a tuple
of
weights and
p,(Xlx
i
-
a)
the
probability
of
detecting the fault f under the condi-
tion of x, - a for a
fixed
value a E {O.I). Applying the
Shannon expansion to the
fa
u
lt
detect
io
n probability
J}
,
(X)
gives
Pf (
X)
- p, {
Xix,
-
0)
- X;"!p,
(X
lx
;-
O)-p
,
(Xlx
r-
i)].
(9)
p, (
X)
depends lin:arly on the input probability x,. For a
tuple
of
weights X ,.,
(x
I"
• " x
;_
!.
XI +
ax
/>
x
r~
I"
.
'.
x~)
with a
quanti~ation
error
~x,
fo
r the weight x;, the fau lt
detection probability
is
Pf{
X)
-
pt<
X)
-
.1.x,.·
[p, (
Xix
; -
0)-
p,(
Xix
; -
1)\
( 10)
"''''
Fi
i.
6.
Test oonfi&uralion ming
TE
..
'>lClllr
.
and using (4) the lest length necessary
10
get the same
probability
of
dctccting all the faults
of
F
is
N(X)"'N(X).pA~)
p
,(
X)
(II)
A small quantization error Jlx
1
docs not significanl-
ly
change the test length as the factor
(p/Xlx
/-
O)
-
p
,(
X
lx,.
- J))/ p,
(X)
is small. This allows the weights
10
be restricted
10
a small
SCI
of
values, e.g
..
(Jj8.2/8,···,7/8).
A procedure to optimize the input
probabilities using only a limited sct
of
different weights
is
described
in
[20].
IV. AROlrr"ECfURE
oFTES
T CH IP
For a complete built-orr lest, patterns must be gener-
ated and applied
10
the CUT, the test responses must
be
collect
ed
and compressed. and t
he
CUT
must be oon-
tro
ll
ed during the whole test execution. All these func-
tions aTC integrated
in
an
AS
IC called
TESTC
HlP
. Fig. 6
shows
the
leSt
configuration. Instead of expensive test
equipment,
only low-cost hardware
is
used.
At
one end
TESTC
HI
P
is
coupled with a personal computer (PC)
or
another
microcomputer that supplies the user interface,
initialiles
the test execution, and evaluates the results. On
the other end
it
is
connected to the
CUT
that
is
provided
with
a scan path (S
Ol
: serial data
in
, SDO: seri
al
data
out).
TESTC
HiP
ge
n
erates
patterns for
th
e primary in-
puts (PI's) and the scan path of the CUT. II controls the
test execution
by
means
of
a clock signal and a mode
control signal (test
mode
or
normal mode
).
Finally.
TESTCH
lP
compresses the test responses from the pri-
mary
outputs
(PO
's) and the scan path
of
the CUT.
A. Programmil/g
WeightS
for Pal/em Gel/eralioll
As a built-off lest using weighted random patterns
is
not intended for just one specific CUT, a hardware pat-
tern
generator
is
required where the weights xi for all the
IEE
E
JOURNAL
Of
SOLlO·~"ATE
CIR
CU
ITS,
VOL
26.
NO
.
7.
JUI.Y IWI
~
.
""'"
.....
ttr
• I (
hi",
)
(II_bet
of
<liuribuliorl)
~"
-
~
(.
upl
~.
0(
-,
""""..,.
_I
(low
)
"
i~j, ~,,)
.--
bi'
pO$itiofI
)
"
,a
"I
~
'"
r:I
~
(
weiJ!u<d
bi.
"
,
f\ltlOUClld
, X
-t
LfSR (
n
fig.
1.
Block
diagram
of
'h
e ",eigh1ed p
se
ud
orandom pallern
genemlOf.
inputs i
i'
j
..
I,' . "
II
, and for
all
the tuples
of
weights
X',
i
~
I,'
",k.,
can
be
programmed independently.
Fig.
7 shows the structure
of
the pattern generator. T
he
modular LFS R with a primitive feedback polynomial forms
the base.
It
s length is chosen sueh that the
state
sequence
does not repeat during the whole test execution.
It
is
tapped at three maximally spaced stages.
There
arc sev·
eral
fe
edback connections between the tap positions. So
the three produced pseudorandom bit sequences at the
outputs ilfe practically independen
t.
To
produce bit se-
quences with weights different from 0.5, these equally
distributcd sequcnces arc combined using the Boolean
functions
/
l!
"
"/7'
The weights are coded
by
3-b
wo
rds and Mored
in
the
RAM. When patterns of width
II
are generated for k
distribution
s,
the KAM must contain
I!·k
3-b words. The
RAM
is
divided into separate sections, one for each
distribution.
The
n weights
of
a distribution arc stored
in
subsequent cells
of
the same section.
The
counter
fo
r thc
lower part
of
the address cycles through the addresses
of
a section. Each
of
these addresses corresponds to a bit
position within the generatcd
pallnn
and selects the
weight programmed for
this bit position. By means
of
the
multiplexer this weight
choo.~es
one
bit
from
the
appropri·
ate weighted bit stream. The Lf SR and the counter
are
clocked
sim
ultaneous
ly
,
Wi
th every clock pulse a weighted
random bit
is
produced, and a new pallern is composed
serially bit
by
bit. This requires much less hardware Ih
an
generating parallel patterns simultaneously.
Ntcr
suffi·
cient
panerns
eorresjxmding
10
the currently used distri-
bution have been generated, the counter for the upper
part
of
the address
is
inc
remented and switches to an-
other sec
ti
on
of
the RAM and th
us
to another tuple
of
weight
s.
B.
HIe Testing Procedure
A more deWiled view
of
TESTCHIP
is
shown
in
f ig.
8.
It contains two completcly separated paltcrn generators
to guarantee that the pseudorandom test patterns
pro-
duced for the primary inputs and the scan path
of
the
CUT are statistically independent. The pattern produced
serially
by
pallern generator 2 is immediately shifted into
th
e scan path. The pattern from pattern generator I
is