International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

Recent advancements in computational inverse-design approaches — algorithmic techniques for discovering optical structures based on desired functional characteristics — have begun to reshape the landscape of structures available to nanophotonics. Here, we outline a cross-section of key developments in this emerging field of photonic optimization: moving from a recap of foundational results to motivation of applications in nonlinear, topological, near-field and on-chip optics. Starting with a desired optical output it is possible to use computational algorithms to inverse design devices. The approach is reviewed here with an emphasis on nanophotonics.

Inverse design in nanophotonics

The phase-shifting mask consists of a normal transmission mask that has been coated with a transparent layer patterned to ensure that the optical phases of nearest apertures are opposite. Destructive interference between waves from adjacent apertures cancels some diffraction effects and increases the spatial resolution with which such patterns can be projected. A simple theory predicts a near doubling of resolution for illumination with partial incoherence σ < 0.3, and substantial improvements in resolution for σ < 0.7. Initial results obtained with a phase-shifting mask patterned with typical device structures by electron-beam lithography and exposed using a Mann 4800 10× tool reveals a 40-percent increase in usuable resolution with some structures printed at a resolution of 1000 lines/mm. Phase-shifting mask structures can be used to facilitate proximity printing with larger gaps between mask and wafer. Theory indicates that the increase in resolution is accompanied by a minimal decrease in depth of focus. Thus the phase-shifting mask may be the most desirable device for enhancing optical lithography resolution in the VLSI/VHSIC era.

Improving resolution in photolithography with a phase-shifting mask

Optical Projection System and Method for Photolithography. A lithographic immersion projection system and method for projecting an image at high resolution over a wide field of view. The projection system and method include a final lens which decreases the marginal ray angle of the optical path before light passes into the immersion liquid to impinge on the image plane.

Projection optical system and method for photolithography and exposure apparatus and method using same

A lithographic apparatus configured to project a patterned beam of radiation onto a target portion of a substrate is disclosed. The apparatus includes a first radiation dose detector and a second radiation dose detector, each detector comprising a secondary electron emission surface configured to receive a radiation flux and to emit secondary electrons due to the receipt of the radiation flux, the first radiation dose detector located upstream with respect to the second radiation dose detector viewed with respect to a direction of radiation transmission, and a meter, connected to each detector, to detect a current or voltage resulting from the secondary electron emission from the respective electron emission surface.

Lithographic apparatus, and device manufacturing method

New degrees of freedom can be optimized in mask shapes
when the source is also adjustable, because required image symmetries can be provided by the source rather than the collected wave front. The optimized mask will often consist of novel sets of shapes that are quite different in layout from the target integrated circuit patterns. This implies that the optimization algorithm should have good global convergence
properties, since the target patterns may not be a suitable starting solution. We have developed an algorithm that can optimize mask and source without using a starting design. Examples are shown where the
process window obtained is between two and six times larger than that achieved with standard reticle enhancement techniques (RET). The optimized
masks require phase shift, but no trim mask is used. Thus far we can only optimize two-dimensional patterns over small fields (periodicities
of ;1 mm or less), though patterns in two separate fields can be jointly optimized for maximum common window under a single source. We also discuss mask optimization with fixed source, source optimization
with fixed mask, and the retargeting of designs in different mask regions to provide a common exposure level.

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Optimum mask and source patterns to print a given shape

Advances in lithography have contributed significantly to the advancement of the integrated circuit technology. While nonoptical next-generation lithography (NGL) solutions are being developed, optical lithography continues to be the workhorse for high-throughput very-large-scale integrated (VLSI) lithography. Extending optical lithography to the resolution levels necessary to support today’s aggressive product road maps increasingly requires the use of resolution-enhancement techniques. This paper presents an overview of several resolution-enhancement techniques being developed and implemented in IBM for its leading-edge CMOS logic and memory products.

TCAD development for lithography resolution enhancement

The grid placement of contacts and gates enables more effective use of resolution enhancement techniques, which in turn allow a reduction of critical dimensions. Although the regular placement adds restrictions during cell layout, the overall circuit area can be made smaller and the extra manufacturing cost can be kept to the lowest by a careful selection of the grid pitch, using template-trim lithography method, allowing random contact placement in the vertical direction, and using rectangular rather than square contacts. The purpose of this work is to optimize the gridded-layout-based process. The trade-off between the layout area and manufacturing cost, and the determination of the minimum grid pitch are discussed in this paper. We demonstrate that it is a 1-D scaling instead of the conventional 2-D scaling for standard cells and the narrow MOSFETs inside after the application of the gridded layout on the contact and gate levels. The corresponding effects on circuit performances, including the leakage current, are also explored.

/pdf/performance-optimization-for-gridded-layout-standard-cells-2jcs0vkzie.pdf

Performance optimization for gridded-layout standard cells

Improvements in the fabrication of integrated circuits are driven by the decrease of the size of the features printed on the wafers. Current lithography techniques limits have been extended through the use of phase-shifting masks, off-axis illumination, and proximity effect correction. More recently, liquid immersion lithography has been proposed as a way to extend even further the limits of optical lithography. This invention described a methodology based on contact printing using a projection lens to define the image of the mask onto the wafer. As the imaging is performed in a solid material, larger refractive indices can be obtained and the resolution of the imaging system can be increased.

Contact printing using a magnified mask image

An optical lithography method is disclosed that uses double exposure of a reusable template mask and a trim mask to fabricate regularly-placed rectangular contacts in standard cells of application-specific integrated circuits (ASICs). A first exposure of the reusable template mask with periodic patterns forms periodic dark lines on a wafer and a second exposure of an application-specific trim mask remove the unwanted part of the dark lines and the small cuts of the dark lines left form the rectangular regularly-placed contacts. All contacts are placed regularly in one direction while unrestrictedly in the perpendicular direction. The regular placement of patterns on the template mask enable more effective use of resolution enhancement technologies, which in turn allows a decrease in manufacturing cost and the minimum contact size and pitch. Since there is no extra application-specific mask needed comparing with the conventional lithography method for unrestrictedly-placed contacts, the extra cost is kept to the lowest. The method of the invention can be used in the fabrication of standard cells in application-specific integrated circuits (ASICs) to improve circuit performance and decrease circuit area and manufacturing cost.

Alfred K. K. Wong

Papers

Optimum mask and source patterns to print a given shape

TCAD development for lithography resolution enhancement

Performance optimization for gridded-layout standard cells

Contact printing using a magnified mask image

Rectangular contact lithography for circuit performance improvement and manufacture cost reduction