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Ali Zahir
Researcher at COMSATS Institute of Information Technology
Publications - 10
Citations - 40
Ali Zahir is an academic researcher from COMSATS Institute of Information Technology. The author has contributed to research in topics: Field-programmable gate array & Control reconfiguration. The author has an hindex of 3, co-authored 10 publications receiving 17 citations.
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Journal ArticleDOI
Towards Low Latency and Resource-Efficient FPGA Implementations of the MUSIC Algorithm for Direction of Arrival Estimation
TL;DR: In this paper, a real-time and resource-efficient implementation of the MUSIC algorithm on Field Programmable Gate Arrays (FPGAs) is proposed, which enables the estimation of DoA in realtime scenarios in $2\mu $ sec with 30% to 50% fewer resources as compared to existing techniques.
Journal ArticleDOI
BPR-TCAM—Block and Partial Reconfiguration based TCAM on Xilinx FPGAs
TL;DR: This paper presents an efficient methodology to implement FPGA-based TCAMs with significant resource savings compared to existing schemes and exploits the fracturable nature of Look Up Tables (LUTs) and the built-in slice carry-chains for simultaneous mapping of two rules and its matching logic to a single FPGAs slice.
Journal ArticleDOI
FracTCAM: Fracturable LUTRAM-Based TCAM Emulation on Xilinx FPGAs
TL;DR: FracTCAM, an efficient methodology for ternary content addressable memory (TCAM) emulation on Xilinx field-programmable gate arrays (FPGAs) by leveraging primitive architectural resources, exploits the fracturable nature of lookup table random access memories (LUTRAMs) and built-in slice flip-flops for deeper pipelining.
Proceedings ArticleDOI
Prototype Designing of Hybrid Power System for Industry with efficient design of Solar Power System
TL;DR: A prototype development of an automatic power changeover switch that is able to switch to the alternative power supply and switch back to the main supply when it is restored and removes the delay caused by manual switching mechanisms is presented.
Proceedings ArticleDOI
Multiple Hash Matching Units (MHMU): An Algorithmic Ternary Content Addressable Memory Design for Field Programmable Gate Arrays
TL;DR: The proposed MHMU scheme exploits the massive parallelism of FPGAs to implement many hash based matching units that use the embedded block RAM memories of the FPGA to reduce the cost of implementing TCAMs.