S
Salvatore Pontarelli
Researcher at University of Rome Tor Vergata
Publications - 183
Citations - 2528
Salvatore Pontarelli is an academic researcher from University of Rome Tor Vergata. The author has contributed to research in topics: Error detection and correction & Network packet. The author has an hindex of 24, co-authored 177 publications receiving 2057 citations. Previous affiliations of Salvatore Pontarelli include Roma Tre University & Télécom ParisTech.
Papers
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Proceedings Article
FlowBlaze: Stateful Packet Processing in Hardware
Salvatore Pontarelli,Roberto Bifulco,Marco Bonola,Carmelo Cascone,Marco Spaziani,Valerio Bruschi,Davide Sanvito,Giuseppe Siracusano,Antonio Capone,Michio Honda,Felipe Huici +10 more
TL;DR: The abstraction FlowBlaze is an open abstraction for building stateful packet processing functions in hardware based on Extended Finite State Machines and introduces the explicit definition of flow state, allowing Flowblaze to leverage flow-level parallelism.
Journal ArticleDOI
Survey of Performance Acceleration Techniques for Network Function Virtualization
Leonardo Linguaglossa,Stanislav Lange,Salvatore Pontarelli,Gábor Rétvári,Dario Rossi,Thomas Zinner,Roberto Bifulco,Michael Jarschel,Giuseppe Bianchi +8 more
TL;DR: This paper provides a comprehensive overview of the host-based network function virtualization (NFV) ecosystem, covering a broad range of techniques, from low-level hardware acceleration and bump-in-the-wire offloading approaches to high-level software acceleration solutions, including the virtualization technique itself.
Journal ArticleDOI
A New Hardware/Software Platform and a New 1/E Neutron Source for Soft Error Studies: Testing FPGAs at the ISIS Facility
Massimo Violante,Luca Sterpone,A. Manuzzato,Simone Gerardin,Paolo Rech,Marta Bagatin,Alessandro Paccagnella,Carla Andreani,Giuseppe Gorini,Antonino Pietropaolo,Gian Carlo Cardarilli,Salvatore Pontarelli,Christopher D. Frost +12 more
TL;DR: A new hardware/software platform for testing SRAM-based FPGAs under heavy-ion and neutron beams, capable of tracing the bit-flips in the configuration memory back to the physical resources affected in the FPGA is introduced.
Journal ArticleDOI
High-Speed Software Data Plane via Vectorized Packet Processing
David Richard Barach,Leonardo Linguaglossa,Damjan Marion,Pierre Pfister,Salvatore Pontarelli,Dario Rossi +5 more
TL;DR: This article introduces the main VPP concepts and architecture, and experimentally evaluates the impact of design choices (such as batch packet processing) on performance.
Journal ArticleDOI
Traffic-Aware Design of a High-Speed FPGA Network Intrusion Detection System
TL;DR: This work promotes a different, traffic-aware, modular approach in the design of FPGA-based NIDS, which classify and group homogeneous traffic, and dispatch it to differently capable hardware blocks, each supporting a (smaller) rule set tailored to the specific traffic category.