Industry is building larger, more complex, manycore processors on the back of strong institutional knowledge, but academic projects face difficulties in replicating that scale. To alleviate these difficulties and to develop and share knowledge, the community needs open architecture frameworks for simulation, synthesis, and software exploration which support extensibility, scalability, and configurability, alongside an established base of verification tools and supported software. In this paper we present OpenPiton, an open source framework for building scalable architecture research prototypes from 1 core to 500 million cores. OpenPiton is the world's first open source, general-purpose, multithreaded manycore processor and framework. OpenPiton leverages the industry hardened OpenSPARC T1 core with modifications and builds upon it with a scratch-built, scalable uncore creating a flexible, modern manycore design. In addition, OpenPiton provides synthesis and backend scripts for ASIC and FPGA to enable other researchers to bring their designs to implementation. OpenPiton provides a complete verification infrastructure of over 8000 tests, is supported by mature software tools, runs full-stack multiuser Debian Linux, and is written in industry standard Verilog. Multiple implementations of OpenPiton have been created including a taped-out 25-core implementation in IBM's 32nm process and multiple Xilinx FPGA prototypes.

https://dl.acm.org/doi/pdf/10.1145/2872362.2872414

OpenPiton: An Open Source Manycore Research Framework

Abstract One of the main aspects of logic synthesis dedicated to FPGA is the problem of technology mapping, which is directly associated with the logic decomposition technique. This paper focuses on using configurable properties of CLBs in the process of logic decomposition and technology mapping. A novel theory and a set of efficient techniques for logic decomposition based on a BDD are proposed. The paper shows that logic optimization can be efficiently carried out by using multiple decomposition. The essence of the proposed synthesis method is multiple cutting of a BDD. A new diagram form called an SMTBDD is proposed. Moreover, techniques that allow finding the best technology mapping oriented to configurability of CLBs are presented. In the experimental section, the presented method (MultiDec) is compared with academic and commercial tools. The experimental results show that the proposed technology mapping strategy leads to good results in terms of the number of CLBs.

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Area-oriented technology mapping for LUT-based logic blocks

Transient faults are a dominant kind of threat to system safety in networked control systems (NCSs) due to their high occurrence rate and wide variety. However, they are hardly detected accurately in NCSs because of their unpredictable nature and short duration. Hence, fault propagation analysis (FPA) has become a bottleneck issue for fault-tolerant control in NCSs, which is used to analyze the fault effects and identify the approximate zone where transient fault occurred. In this paper, an innovative ontology-based FPA approach (ontologyFPA) is proposed to analyze transient fault propagation effects in NCSs. From the view of object-centered ontology, function, behavior, and structure models are built to reflect system abstraction hierarchies, and fault propagation effects and traces are identified from behaviors to functions through the mapping relationships of abstraction models. From the view of system-centered ontology, information-based workflows are employed to represent system independence in which fault propagation is investigated by excavating different effect traces among serial tasks in control loops. To illustrate the processes of propagation analysis, the application of ontologyFPA in a steam generator water level control system is presented. Finally, based on a unified simulation platform described by the architecture analysis and design language (AADL), two types of faults are injected to inspect the fault propagation processes between abstraction hierarchies, while another type is injected to investigate the processes in workflows. The results demonstrate that the proposed approach is effective in terms of identifying transient fault propagation effects and traces.

A Class of General Transient Faults Propagation Analysis for Networked Control Systems

The fault-tolerant character of WSN protocols and applications that do not assume completely reliable systems legitimize undervolting - a highly efficient energy management technique where the supply voltage is set below the minimum specifications. As has been shown in earlier work, by using thereliable IdealVolting undervolting scheme the lifetime of WSN applications can be increased significantly while keeping the node in a safe state even under rough environmental conditions. To show the usability of undervolting in a real world WSN deployment, we performed a long-term study of IdealVolting in a Smart Farming application. All measurements were performed on a generic outdoor testbed for WSNs (PotatoNet) which is also presented within this paper. We collected a long-term dataset of a WSN running for one farming season on a potato fieldto compare the reliability and performance characteristics of IdealVolting against a regular powered WSN.

Undervolting in Real World WSN Applications: A Long-Term Study

Adapting the voltage level of a processing unit to the actual system load leads to an increased energy efficiency. The aim is to extend the battery lifetime, but existing voltage scaling approaches still act with reserve. To reduce the energy consumption even further, it is possible to power the electric circuits below the specified voltage levels. Considering the processing unit of wireless sensor nodes, this “undervolting” saves up to 42% of energy per clock cycle, and hence would lead to a significant longer lifetime of nodes and networks. Contrariwise, operating processors or nodes outside their specifications add some extra incertitude to the system. In this paper, we analyze the effects of undervolting for a typical wireless sensor node in theory and practice. Moreover, we give a detailed insight into the dependencies and used a prototype implementation to characterize the influence of lower than recommended voltage levels on the microcontroller unit (MCU). In addition, the impact of different temperatures is considered as well as the behavior of an undervolted transceiver unit and, therefore, the effects on the wireless communication. While classical computer applications may contain too many hazards to outweigh the improved energy consumption when using undervolting, we show that it is particularly suitable for wireless sensor networks (WSNs) with a huge potential of saving energy and the opportunity of novel power management approaches on every layer.

Undervolting in WSNs: Theory and Practice

This paper presents an analysis of the effects and propagations of transient faults by simulation-based fault injection into the AVR microcontroller. This analysis is done by injecting 20000 transient faults into main components of the AVR microcontroller that is described in VHDL language. The sensitivity level of various points of the AVR microcontroller such as ALU, Instruction-Register, Program-Counter, Register-file and Flag Registers against fault manifestation is considered and evaluated. The behavior of AVR microcontroller against injected faults is reported and shown that about 41.46% of faults are recovered in simulation time, 53.84% of faults are effective faults and reminding 4.70% of faults are latent faults; moreover a comparison of the behavior of AVR microcontroller in fault injection experiments against some common microprocessors is done. Results of fault analyzing will be used in the future research to propose the fault-tolerant AVR microcontroller.

An Analysis of Fault Effects and Propagations in AVR Microcontroller ATmega103(L)

this paper proposes a new reconfigurable architecture for Configuration Logic Block (CLB) in SRAM-based FPGAs. This architecture can correct Single Event Upset (SEU) by utilizing both Triple Modular Redundancy (TMR) and mapping technique. Since the proposed architecture can implement all the k-input Boolean functions, it can be used instead of Look-Up Table (LUT) in current-day SRAM-based FPGAs; moreover, the proposed architecture uses the same routing architecture which is presented in current-day FPGAs, so all CAD algorithms can be used in the employed design. Experimental results show that the proposed architecture can correct 100% SEU in the configuration memory of CLB without any user intervention or reconfiguration; moreover, the required area and the power consumption are respectively 136% and 195% more than the area and the power consumption that are required by the standard 16 ×1 LUT.

A New CLB Architecture for Tolerating SEU in SRAM-Based FPGAs

Two effective methods to mitigate soft error effects in SRAM-based FPGAs

This paper proposes three methods to mitigate and tolerate SEU-caused errors on the configuration bits of SRAM-based field programmable gate arrays. The proposed methods are based on error detection and correction codes which are able to detect or correct SEU-caused errors in Switch Modules. The effects of proposed methods on the various parameters such as area, delay and power consumption for ten ITC'99 benchmark circuits have been evaluated with synopsis® CAD tool and compared with previous work. The experimental results show that the proposed methods can detect or correct 100% single errors in Switch Modules by imposing area overhead between 2% and 60%, delay overhead between 25% and 100% and power consumption overhead between 1% and 25%.

Mitigating and tolerating SEU effects in switch modules of SRAM-based FPGAs

This paper presents an analysis of the effects and propagations of transient faults by simulation-based fault injection into the ZPU processor. This analysis is done by injecting 5800 transient faults into the main components of ZPU processor that is described in VHDL language. The sensitivity level of various points of ZPU processor such as PC, SP, IR, Controller, and ALU against fault manifestation is considered and evaluated. The behavior of ZPU processor against injected faults is reported. Besides, it is shown that about 50.25% of faults are recovered during simulation time; 46.47% of faults are effective and the remainders 3.28% of faults are latent. Moreover, a comparison of the behavior of ZPU processor in fault injection experiments against some common microprocessors is done. The results will be used in the future research for proposing a fault-tolerant mechanism for ZPU processor.

Alireza Rohani

Papers

An Analysis of Fault Effects and Propagations in AVR Microcontroller ATmega103(L)

A New CLB Architecture for Tolerating SEU in SRAM-Based FPGAs

Two effective methods to mitigate soft error effects in SRAM-based FPGAs

Mitigating and tolerating SEU effects in switch modules of SRAM-based FPGAs

An analysis of fault effects and propagations in ZPU: The world's smallest 32 bit CPU