Approximate computing has recently emerged as a promising approach to energy-efficient design of digital systems. Approximate computing relies on the ability of many systems and applications to tolerate some loss of quality or optimality in the computed result. By relaxing the need for fully precise or completely deterministic operations, approximate computing techniques allow substantially improved energy efficiency. This paper reviews recent progress in the area, including design of approximate arithmetic blocks, pertinent error and quality measures, and algorithm-level techniques for approximate computing.

/pdf/approximate-computing-an-emerging-paradigm-for-energy-z7hetfdl3q.pdf

Approximate computing: An emerging paradigm for energy-efficient design

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私の computer 環境

https://ris.utwente.nl/ws/files/13291952/FTA_overview.pdf

Fault tree analysis

Stochastic computing (SC) was proposed in the 1960s as a low-cost alternative to conventional binary computing. It is unique in that it represents and processes information in the form of digitized probabilities. SC employs very low-complexity arithmetic units which was a primary design concern in the past. Despite this advantage and also its inherent error tolerance, SC was seen as impractical because of very long computation times and relatively low accuracy. However, current technology trends tend to increase uncertainty in circuit behavior and imply a need to better understand, and perhaps exploit, probability in computation. This article surveys SC from a modern perspective where the small size, error resilience, and probabilistic features of SC may compete successfully with conventional methodologies in certain applications. First, we survey the literature and review the key concepts of stochastic number representation and circuit structure. We then describe the design of SC-based circuits and evaluate their advantages and disadvantages. Finally, we give examples of the potential applications of SC and discuss some practical problems that are yet to be solved.

/pdf/survey-of-stochastic-computing-10orkcfmr8.pdf

Survey of Stochastic Computing

From the Publisher:
Real-Time Systems is both a valuable reference for professionals and an advanced text for Computer Science and Computer Engineering students. 

Real world real-time applications based on research and practice

State-of-the-art algorithms and methods for validation

Methods for end-to-end scheduling and resource management

More than 100 illustrations to enhance understanding

Comprehensive treatment of the technology known as RMA (rate-monotonic analysis) methods

A supplemental Companion Website www.prenhall.com/liu

http://user.it.uu.se/~yi/courses/rts/dvp-rts-08/notes/Course-INFO.pdf

Real-Time Systems

This paper presents a fault injection tool called SINJECT that supports several synthesizable and non-synthesizable fault models for dependability analysis of digital systems modeled by popular HDLs. The tool provides injection of transient and permanent faults into the Verilog as well as VHDL models of a digital circuit to study the fault behavior, fault propagation and fault coverage. Moreover, using specific simulators, the SINJECT provides a mixed-mode fault injection, i.e., fault injection into both Verilog and VHDL parts of a model, to achieve high description reality by Verilog and high capability modeling by VHDL. To demonstrate the tool, two case studies are evaluated: (1) an arithmetic processor with a non-synthesizable Verilog model, called ARP; and (2) a VHDL model of 32-bit processor with a synthesizable ALU, called DP32. The results show that depending on the fault injection points in the ARP, the effects of faults were significantly different, while in the case of DP32, the fault coverage varied between 51 to 56 percent of total faults injected.

Dependability analysis using a fault injection tool based on synthesizability of HDL models

This paper presents a high level method called Matrix code to protect SRAM-based memories against multiple bit upsets. The proposed method combines hamming code and parity code to assure the reliability of memory in presence of multiple bit-upsets with low area and performance overhead. The method is evaluated using one million multiple-fault injection experiments; next reliability and MTTF of the protected memories are estimated based on fault injection experiments and several equations. The fault detection/correction coverage are also calculated and compared with previous methods i.e., Reed-Muller and hamming code. The results reveal that the proposed method behaves better than these methods in terms of fault detection and correction of multiple faults regarding to the area overhead.

Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories

This paper presents a high level error detection and correction method called HVD code to tolerate multiple bit upsets (MBUs) occurred in memory cells. The proposed method uses parity codes in four directions in a data part to assure the reliability of memories. The proposed method is very powerful in error detection while its error correction coverage is also acceptable considering its low computing latency. HVD code is useful for applications whose high error detection coverage is very important such as memory systems. Of course, this code can be used in combination with other protection codes which have high correction coverage and low detection coverage. The proposed method is evaluated using more than one billion multiple fault injection experiments. Multiple bit flips were randomly injected in different segments of a memory system and the fault detection and correction coverages are calculated. Results show that 100% of the injected faults can be detected. We proved that, this method can correct up to three bit upsets. Some hardware implementation issues are investigated to show tradeoffs between different implementation parameters of HVD method.

HVD: horizontal-vertical-diagonal error detecting and correcting code to protect against with soft errors

This paper presents a method based on stochastic logic to analyse fault trees. This method supports both static and dynamic gates, and can be applied to any type of fault trees. In this paper, static and dynamic gates would be translated into stochastic logic templates, and a hardware implementation for each gate would be achieved. Based on these hardware templates, it is possible to implement the whole logic on a Field-Programmable Gate Array (FPGA). Utilizing the stochastic logic for implementing a given fault tree on FPGA, the analysis would outperform the following parameters compared to traditional methods: 1) Speed-up, 2) Simplicity, 3) Reliability, and 4) Accuracy. Experimental results illustrate that using stochastic logic for modeling fault trees results in fast convergence of Monte Carlo simulation. Moreover, on average, our FPGA approach takes 50% of the time required by previous emulation approaches. Simplicity is an additional advantage of the proposed approach, achieved because of simplicity behind stochastic logic. Also, the stochastic logic is more reliable compared to traditional logic because any faults like SEUs in stochastic logic have less impact on the whole results compared to traditional arithmetic logic. To evaluate the proposed technique, the analysis is performed on several standard benchmarks composed of static and dynamic gates. The results obtained using this approach agree with those obtained from an analytical approach, which proves that the method is an accurate tool for system reliability modeling.

A Fast and Accurate Fault Tree Analysis Based on Stochastic Logic Implemented on Field-Programmable Gate Arrays

This paper presents a new fault injection approach, which is based on a co-operation between a simulator and an emulator. This hybrid approach utilizes the advantages of both simulation-based fault injection as well as physical fault injection to provide a good controllability, observability and also a high speed in the fault injection experiments. To do this, parts of a circuit are simulated while the rest parts of the circuit are emulated. A fault injection tool called FITSEC (Fault Injection Tool based on Simulation and Emulation Cooperation) is developed, which supports the entire process of a system design. This is based on both Verilog and VHDL languages and can be used to inject faults at different levels of abstraction. The experimental results show that this approach can significantly reduce the time needed for executing fault injection campaigns.

Hamid R. Zarandi

Papers

Dependability analysis using a fault injection tool based on synthesizability of HDL models

Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories

HVD: horizontal-vertical-diagonal error detecting and correcting code to protect against with soft errors

A Fast and Accurate Fault Tree Analysis Based on Stochastic Logic Implemented on Field-Programmable Gate Arrays

A hybrid fault injection approach based on simulation and emulation co-operation