Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

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Fundamentals of Modern VLSI Devices

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

To provide a semiconductor device and a display device which can be manufactured through a simplified process and the manufacturing technique. Another object is to provide a technique by which a pattern of wirings or the like which is partially constitutes a semiconductor device or a display device can be formed with a desired shape with controllability.

Semiconductor device, electronic device, and method of manufacturing semiconductor device

Known elementary wide-band amplifiers suffer from a fundamental tradeoff between noise figure (NF) and source impedance matching, which limits the NF to values typically above 3 dB. Global negative feedback can be used to break this tradeoff, however, at the price of potential instability. In contrast, this paper presents a feedforward noise-canceling technique, which allows for simultaneous noise and impedance matching, while canceling the noise and distortion contributions of the matching device. This allows for designing wide-band impedance-matching amplifiers with NF well below 3 dB, without suffering from instability issues. An amplifier realized in 0.25-/spl mu/m standard CMOS shows NF values below 2.4 dB over more than one decade of bandwidth (i.e., 150-2000 MHz) and below 2 dB over more than two octaves (i.e., 250-1100 MHz). Furthermore, the total voltage gain is 13.7 dB, the -3-dB bandwidth is from 2 MHz to 1.6 GHz, the IIP2 is +12 dBm, and the IIP3 is 0 dBm. The LNA drains 14 mA from a 2.5-V supply and the die area is 0.3/spl times/0.25 mm/sup 2/.

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Wide-band CMOS low-noise amplifier exploiting thermal noise canceling

The phase-shifting mask consists of a normal transmission mask that has been coated with a transparent layer patterned to ensure that the optical phases of nearest apertures are opposite. Destructive interference between waves from adjacent apertures cancels some diffraction effects and increases the spatial resolution with which such patterns can be projected. A simple theory predicts a near doubling of resolution for illumination with partial incoherence σ < 0.3, and substantial improvements in resolution for σ < 0.7. Initial results obtained with a phase-shifting mask patterned with typical device structures by electron-beam lithography and exposed using a Mann 4800 10× tool reveals a 40-percent increase in usuable resolution with some structures printed at a resolution of 1000 lines/mm. Phase-shifting mask structures can be used to facilitate proximity printing with larger gaps between mask and wafer. Theory indicates that the increase in resolution is accompanied by a minimal decrease in depth of focus. Thus the phase-shifting mask may be the most desirable device for enhancing optical lithography resolution in the VLSI/VHSIC era.

Improving resolution in photolithography with a phase-shifting mask

The impact of scaling on the analog performance of MOS devices at RF frequencies was studied. Trends in the RF performance of nominal gate length NMOS devices from 350-nm to 50-nm CMOS technologies are presented. Both experimental data and circuit simulations with an advanced validated compact model (MOS Model 11) have been used to evaluate the RF performance. RF performance metrics such as the cutoff frequency, maximum oscillation frequency, power gain, noise figure, linearity, and 1 noise were included in the analysis. The focus of the study was on gate and drain bias conditions relevant for RF circuit design. A scaling methodology for RF-CMOS based on limited linearity degradation is proposed.

https://www.nxp.com/wcm_documents/models/mos-models/model-11/woe2001_ted.pdf

RF-CMOS Performance Trends

Extensive measurements of drain current thermal noise are presented for 3 different CMOS technologies and for gate lengths ranging from 2 /spl mu/m down to 0.17 /spl mu/m. Using a surface-potential-based compact MOS model with improved descriptions of carrier mobility and velocity saturation, all the experimental results can be described accurately without invoking carrier heating effects or introducing additional parameters.

Accurate thermal noise model for deep-submicron CMOS

This paper presents new insights into the mechanisms of gate depletion and boron penetration in deep submicron CMOS technologies MOSFET matching measurements show that these effects are stochastic in nature, and are associated with the gate poly-Si grain size distribution Moreover, this work demonstrates that these effects can strongly degrade transistor matching performance of future CMOS generations

Effects of gate depletion and boron penetration on matching of deep submicron CMOS transistors

In a method of manufacturing a semiconductor device comprising a field-effect transistor and a non-volatile memory element at a surface of a semiconductor body, a first and a second active region of a first conductivity type are defined at the surface of the semiconductor body for the transistor and the memory element, respectively. The surface of the semiconductor body is subsequently coated with a first insulating layer providing a sacrificial gate dielectric of the transistor and a floating gate dielectric of the memory element, which first insulating layer is then covered by a silicon-containing layer providing a sacrificial gate of the transistor and a floating gate of the memory element. After formation of the sacrificial gate and the floating gate, the transistor and the memory element are provided with source and drain zones of a second conductivity type. In a next step, a dielectric layer is applied, which is removed over at least part of its thickness by means of a material removing treatment until the silicon-containing layer at the first and the second active region and is exposed, after which the silicon-containing first active region are removed, thereby forming a recess in the dielectric layer. Subsequently, a second insulating layer is applied at the second active region providing an inter-gate dielectric of the memory element, and a third insulating layer is applied at the first active region providing a gate dielectric of the transistor. After formation of the gate dielectric and the inter-gate dielectric, a conductive layer is applied which is shaped into a gate of the transistor at the first active region and a control gate of the memory element at the second active region.

Method of manufacturing a nonvolatile memory

The authors describe a 252 mu m/sup 2/ bulk full CMOS SRAM cell for application in high-density static memories fabricated in a 14-mask process using minimum dimensions of 05 mu m at a comparatively relaxed 12 mu m pitch A very aggressive n/sup +//p/sup +/ spacing and a fully overlapping contact technology are the key elements used to achieve a competitive cell area The functionality of the cell was shown on a 1 kb test memory >

Andreas H. Montree

Papers

RF-CMOS Performance Trends

Accurate thermal noise model for deep-submicron CMOS

Effects of gate depletion and boron penetration on matching of deep submicron CMOS transistors

Method of manufacturing a nonvolatile memory

A 25 mu m/sup 2/ bulk full CMOS SRAM cell technology with fully overlapping contacts