The speed of VLSI chips is increasingly limited by signal delay in long interconnect lines. A simple analysis shows that major speed improvements are possible when using current-mode rather than conventional voltage-mode signal transporting techniques. The key to this approach is the use of low-resistance current-signal circuits to drastically reduce the impedance level and the voltage swings on long interconnect lines. As an example, a simple four-transistor current-sense amplifier for fast CMOS SRAMs is proposed. The circuit presents a virtual short circuit to the bit lines, thus reducing the sensing delay, which is rendered practically insensitive to the bit-line capacitance. In addition, the virtual short circuit ensures equal bit-line voltages, thus eliminating the need for bit-line equalization during a read access. >

Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM's

After defining the multiplication factor and the ionization rate together with their interrelationship, multiplication and breakdown models for diodes and MOS transistors are discussed. Different ionization models are compared and test structures are discussed for measuring the multiplication factor accurately enough for reliable extraction of the ionization rates. Multiplication measurements at different temperatures are performed on a bipolar NPN transistor, and yield new electron ionization rates at relatively low electrical fields. An explanation for the spread of the experimental values of the existing data on ionization rate is given. A new implementation method for a local avalanche model into a device simulator is presented. The results are less sensitive to the chosen grid size than the ones obtained from the existing method.

/pdf/impact-ionization-in-silicon-a-review-and-update-2nmz801knv.pdf

Impact ionization in silicon: A review and update

Design and processing concepts are presented that have led to the development of rugged high-current (100 A range) low-voltage trench DMOS transistors, featuring 4 mΩ on-resistance, with controlled bulk avalanche breakdown at 70 V and gate dielectric breakdown at 60 V. The results of a simulation-based investigation are also presented, revealing that the trench DMOS technology has at least a factor-of-two die area advantage over its planar DMOS counterpart in the range from low (50 V) to medium (200 V) voltages.

Trench DMOS transistor technology for high-current (100 A range) switching

The present state of understanding of the dynamics of magnetic domain walls and magnetic bubbles is reviewed The theory of domain wall motion for the linear and non-linear regions is outlined Experimental techniques for straight walls and magnetic bubbles are discussed An extensive comparison between theory and experiment is made Topics included are peak and saturation velocities, mobility, inertial effects and overshoot, hard bubbles, wall states and state transformations in magnetic bubbles Origins of wall damping are also discussed

http://iopscience.iop.org/article/10.1088/0034-4885/43/6/001/pdf

Dynamic properties of magnetic domain walls and magnetic bubbles

The most commonly used high-voltage blocking and termination structures-floating field limiting rings (FLR), lateral charge control HVIC devices, and junction termination extension (JTE) structures-are very sensitive to positive silicon and silicon dioxide interface charges. These high-voltage termination structures specifically designed for 1000-V blocking capability lose 25 to 50% of their voltage-blocking capability under 5*10/sup 11/ cm/sup -2/ net interface state density. In contrast, optimized multiple-zone JTE (MZ-JTE), and offset multiple field plated and field-limiting ring (OFP-FLR) structures will lose only 5% of their respective voltage blocking capabilities under the same surface-charge condition. These improved high-voltage blocking structures do not require additional passivation and process complexities. >

Optimization and surface charge sensitivity of high-voltage blocking structures with shallow junctions

A quantitative model for the time behaviour of the walk-out phenomenon in planar p - n junctions is given. The injection of hot carriers into SiO 2 and subsequent trapping of part of them is assumed to be the origin of the walk-out. The model is found to be in reasonable agreement with the experimental results on both p + − n and n + − p junctions. The parameters in the model are discussed in relation with the experiments.

Drift of the breakdown voltage in p-n junctions in silicon (walk-out)

The authors describe a 252 mu m/sup 2/ bulk full CMOS SRAM cell for application in high-density static memories fabricated in a 14-mask process using minimum dimensions of 05 mu m at a comparatively relaxed 12 mu m pitch A very aggressive n/sup +//p/sup +/ spacing and a fully overlapping contact technology are the key elements used to achieve a competitive cell area The functionality of the cell was shown on a 1 kb test memory >

A 25 mu m/sup 2/ bulk full CMOS SRAM cell technology with fully overlapping contacts

A high performance CMOS technology has been developed for application in very fast circuits. A 1 Mb SRAM with 6 transistor cells was designed /1/ end processed. Figure 1 shows a photograph of the completed chip. The insert is a magnification of the corresponding corner. In table 1 the most important design rules are listed with a summary of the technology and some data of the memory. The technology contains 0. 7 µm lithographic dimensions. Important features are: tight field isolation (1.0 µm) achieved by a special masking and oxidation procedure /2/, twin retrograde wells to provide high parasitic threshold and punch throughout voltages and an extremely small n+ to p+ spacing of 2. 5 µm. Latch-up is sufficiently suppressed by the use of thin p-/p+ epi material. The gate oxide thickness is 17.5 nm. Both n-channel and p-channel MOSTs contain an LDD structure. A strap technology is used to realize buried contacts and local interconnect. Ti salicide technology and double level metal offer a low resistance interconnect. Planarization is applied throughout the process.

A 1M SRAM with full CMOS cells fabricated in a 0.7&#181;m technology

A high-frequency current-access output gate is applied to a field-access memory operating at lower frequencies. This takes advantage of materials whose maximum velocity is not reached at the obtainable rotating-field frequency. The access and cycle times can decrease easily by a factor of 2 to 6. A number of elements has been designed, necessary to perform a combination of field-access and current-access circuits. Conductor propagation structures and field-current transfer gates have been tested on high mobility 7μm-bubble La, Ga-YIG. These elements, though not optimised, already have overlapping margins. Single-mask conductors consisting entirely of permalloy or a sandwich of permalloy on gold both propagate bubbles up to about 1 MHz frequency.

Combination of field and current access magnetic bubble circuits

In this paper we present a complete process for field isolation applicable in a submicron CMOS process as will be needed for future VLSI.

R. de Werdt

Papers

Drift of the breakdown voltage in p-n junctions in silicon (walk-out)

A 25 mu m/sup 2/ bulk full CMOS SRAM cell technology with fully overlapping contacts

A 1M SRAM with full CMOS cells fabricated in a 0.7µm technology

Combination of field and current access magnetic bubble circuits

Field Isolation Process for Submicron CMOS

R. de Werdt

Papers

Drift of the breakdown voltage in p-n junctions in silicon (walk-out)

A 25 mu m/sup 2/ bulk full CMOS SRAM cell technology with fully overlapping contacts

A 1M SRAM with full CMOS cells fabricated in a 0.7&#181;m technology

Combination of field and current access magnetic bubble circuits

Field Isolation Process for Submicron CMOS

A 1M SRAM with full CMOS cells fabricated in a 0.7µm technology