A
Andrew Lines
Researcher at Intel
Publications - 21
Citations - 2772
Andrew Lines is an academic researcher from Intel. The author has contributed to research in topics: Asynchronous communication & Asynchronous system. The author has an hindex of 13, co-authored 21 publications receiving 1713 citations.
Papers
More filters
Journal ArticleDOI
Loihi: A Neuromorphic Manycore Processor with On-Chip Learning
Michael Davies,Narayan Srinivasa,Tsung-Han Lin,Gautham N. Chinya,Cao Yongqiang,Sri Harsha Choday,Georgios D. Dimou,Prasad Joshi,Nabil Imam,Shweta Jain,Yuyun Liao,Chit-Kwan Lin,Andrew Lines,Ruokun Liu,Deepak A. Mathaikutty,Steven McCoy,Arnab Paul,Jonathan Tse,Guruguhanathan Venkataramanan,Yi-Hsin Weng,Andreas Wild,Yoon Seok Yang,Hong Wang +22 more
TL;DR: Loihi is a 60-mm2 chip fabricated in Intels 14-nm process that advances the state-of-the-art modeling of spiking neural networks in silicon, and can solve LASSO optimization problems with over three orders of magnitude superior energy-delay-product compared to conventional solvers running on a CPU iso-process/voltage/area.
Patent
Logic synthesis of multi-level domino asynchronous pipelines
TL;DR: In this paper, a gate level circuit description corresponding to the circuit design is generated, and a minimal number of buffers are added to selected ones of the pipelines such that a performance constraint is satisfied.
Patent
Asynchronous system-on-a-chip interconnect
Uri Cummings,Andrew Lines +1 more
TL;DR: In this article, the authors describe a system-on-a-chip (SOC) which includes a plurality of synchronous modules, each synchronous module having an associated clock domain characterized by a data rate.
Patent
Asynchronous static random access memory
Uri Cummings,Andrew Lines +1 more
TL;DR: In this article, a static random access memory (SRAM) is provided including a plurality of SRAM state elements and SRAM environment circuitry, which is operable to interface with external asynchronous circuitry and to enable reading of and writing to the state elements in a delay-insensitive manner.
Patent
Shared-memory switch fabric architecture
TL;DR: In this paper, a shared memory is described as having a plurality of receive ports with a first-and a second-data-rate memory array, and buffering is used to decouple operation of the receive and transmit ports at the first data rate from operation of memory array at the second-and third-data rates.