Georgios D. Dimou

TL;DR: Loihi is a 60-mm2 chip fabricated in Intels 14-nm process that advances the state-of-the-art modeling of spiking neural networks in silicon, and can solve LASSO optimization problems with over three orders of magnitude superior energy-delay-product compared to conventional solvers running on a CPU iso-process/voltage/area.

TL;DR: In this article, the authors present methods, apparatuses, and systems for performing data encoding involving encoding data bits according to an outer convolutional code to produce outer encoded bits processing the inner encoded bits using an interleaver and a logical unit to produce intermediate bits, wherein the logical unit receives a first number of input bits and produces a second number of corresponding output bits, the second number being less than the first number.

TL;DR: This paper suggests a new class of TLCs that is called systematic with serially concatenated parity (S-SCP) codes, one of which is the Generalized (or Systematic) repeat accumulate code and describes two other members of this family that both exhibit good performance over a wide range of block sizes, code rates, modulation, and target error probability.

TL;DR: In this article, a tree-structured soft-in/soft-output (SISO) module is used to compute forward and backward state metrics of the received input signal using a tree structure.

TL;DR: The design of a commercially-shipping 72-port 10G Ethernet switch router integrated circuit is presented, which relied heavily on a novel tool flow utilizing both commercial and proprietary EDA tools for automatic place-and-route of asynchronous layout.