International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

This paper presents HotSpot-a modeling methodology for developing compact thermal models based on the popular stacked-layer packaging scheme in modern very large-scale integration systems. In addition to modeling silicon and packaging layers, HotSpot includes a high-level on-chip interconnect self-heating power and thermal model such that the thermal impacts on interconnects can also be considered during early design stages. The HotSpot compact thermal modeling approach is especially well suited for preregister transfer level (RTL) and presynthesis thermal analysis and is able to provide detailed static and transient temperature information across the die and the package, as it is also computationally efficient.

/pdf/hotspot-a-compact-thermal-modeling-methodology-for-early-43x1muqtv2.pdf

HotSpot: a compact thermal modeling methodology for early-stage VLSI design

IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

With the rapid developments in very large-scale integration (VLSI) technology, design and computer-aided design (CAD) techniques, at both the chip and package level, the operating frequencies are fast reaching the vicinity of gigahertz and switching times are getting to the subnanosecond levels. The ever increasing quest for high-speed applications is placing higher demands on interconnect performance and highlighted the previously negligible effects of interconnects such as ringing, signal delay, distortion, reflections, and crosstalk. In this review paper various high-speed interconnect effects are briefly discussed. In addition, recent advances in transmission line macromodeling techniques are presented. Also, simulation of high-speed interconnects using model-reduction-based algorithms is discussed in detail.

/pdf/simulation-of-high-speed-interconnects-4k5dt3lsur.pdf

Simulation of high-speed interconnects

Preparing the books to read every day is enjoyable for many people. However, there are still many people who also don't like reading. This is a problem. But, when you can support others to start reading, it will be better. One of the books that can be recommended for new readers is computer aided analysis of electronic circuits algorithms and computational techniques. This book is not kind of difficult book to read. It can be read and understand by the new readers.

Computer-aided analysis of electronic circuits: Algorithms and computational techniques

Leakage power is emerging as a key design challenge in current and future CMOS designs. Since leakage is critically dependent on operating temperature and power supply, we present a full chip leakage estimation technique which accurately accounts for power supply and temperature variations. State of the art techniques are used to compute the thermal and power supply profile of the entire chip. Closed-form models are presented which relate leakage to temperature and VDD variations. These models coupled with the thermal and VDD profile are used to generate an accurate full chip leakage estimation technique considering environmental variations. The results of this approach are demonstrated on large-scale industrial designs.

/pdf/full-chip-leakage-estimation-considering-power-supply-and-4am1rf1wjw.pdf

Full chip leakage-estimation considering power supply and temperature variations

Static timing analysis is a critical step in design of any digital integrated circuit. Technology and design trends have led to significant increase in environmental and process variations which need to be incorporated in static timing analysis. This paper presents a new, efficient and accurate block-based static timing analysis technique considering uncertainty. This new method is more efficient as its models arrival times as cumulative density functions (CDFs) and delays as probability functions (PDFs). Computationally simple expression are presented for basic static timing operations. The techniques are valid for any form of the probability distribution, though the use piecewise linear modeling of CDFs is highlighted in this paper. Reconvergent fanouts are handled using a new technique that avoids path tracing. Variable accuracy timing analysis can be performed by varying the modeling accuracy of the piecewise linear model. Regular and statistical timing on different parts of the circuit can be incorporated into a single timing analysis run. Accuracy and efficiency of the proposed method is demonstrated for various ISCAS benchmark circuits.

/pdf/block-based-static-timing-analysis-with-uncertainty-2pyyg8t0ib.pdf

Block-based Static Timing Analysis with Uncertainty

Buffer insertion seeks to place buffers on the wires of a signal netto minimize delay. Van Ginneken [Buffer Placement in Distributed RC-tree Networks for Minimal Elmore Delay] proposed an optimal dynamicprogramming solution (with extensions proposed by [7] [8][9] [12]) such that at most one buffer can be placed on a singlewire. This constraint can hurt solution quality, but it may be circumventedby dividing each wire into multiple smaller segments.This work studies the problem of finding the correct number of segmentsfor each wire in the routing tree. Too few segments yieldssub-par solutions, but too many segments can lead to excessive runtimes and memory loads. We derive new theoretical results forcomputing the appropriate number of buffers (and hence wire segments)which motivate our new wire segmenting algorithm. Weshow that using wire segmenting as a precursor to buffer insertionproduces solutions within a few percent of optimal, while usingonly seconds of CPU time.

http://www.cecs.uci.edu/~papers/compendium94-03/papers/1997/dac97/pdffiles/37_1.pdf

Wire segmenting for improved buffer insertion

Noise analysis and avoidance is an increasingly critical step in deep submicron design. Ever increasing requirements on performance have led to widespread use of dynamic logic circuit families and its other derivatives. These aggressive circuit families trade off noise margin for timing performance making them more susceptible to noise failure and increasing the need for noise analysis. Currently, noise analysis is performed either through circuit or timing simulation or through model order reduction. These techniques in use are still inefficient for analyzing massive amount of interconnect data found in present day integrated circuits. This paper presents efficient techniques for estimation of coupled noise in on-chip interconnects. This noise estimation metric is an upper bound for RC circuits, being similar in spirit to Elmore delay in timing analysis. Such an efficient noise metric is especially useful for noise criticality pruning and physical design based noise avoidance techniques.

/pdf/efficient-coupled-noise-estimation-for-on-chip-interconnects-h44ovl1asz.pdf

Efficient coupled noise estimation for on-chip interconnects

On-chip inductance extraction and analysis is becoming increasing critical. Inductance extraction can be difficult, cumbersome and impractical on large designs as inductance depends on the current return path -- which is typically unknown prior to extracting and simulating the circuit model. In this paper, we propose a new circuit element, K, to model inductance effects, at the same time being easier to extract and analyze. K is defined as inverse of partial inductance matrix L, and has locality and sparsity normally associated with a capacitance matrix. We propose to capture inductance effects by directly extracting and simulating K, instead of partial inductance, leading to much more efficient procedure which is amenable to full chip extraction. This proposed approach has been verified through several simulation results.

Anirudh Devgan

Papers

Full chip leakage-estimation considering power supply and temperature variations

Block-based Static Timing Analysis with Uncertainty

Wire segmenting for improved buffer insertion

Efficient coupled noise estimation for on-chip interconnects

How to efficiently capture on-chip inductance effects: introducing a new circuit element K