A thyristor-based memory may comprise a thyristor accessible via an access transistor. A temperature dependent bias may be applied to at least one of a supporting substrate and an electrode capacitively-coupled to a base region of the thyristor. The voltage level of the adaptive bias may change with respect to temperature and may influence and/or compensate an inherent bipolar gain of the thyristor in accordance with the change in bias and may enhance its performance and/or reliability over a range of operating temperature. In a particular embodiment, the thyristor may be formed in a layer of silicon of an SOI substrate and the adaptive bias coupled to a supporting substrate of the SOI structure.

Thyristor-based memory and its method of operation

This paper presents a direct conversion, multistandard TV tuner implemented on a 65 nm digital CMOS process occupying less than 7 . The tuner is compliant with several digital terrestrial, fixed and mobile TV standards, including DVB-T, DVB-H, T-DMB, and ISDB-T. It achieves a 3/3.2/3.5 dB noise figure at VHF, UHF, and L-band, respectively, while the measured sensitivity at UHF for the QPSK-frac12 DVB-T mode is at the PCB connector. The implemented RF front-ends support both single-ended and differential inputs. An integrated - fractional-N synthesizer operating from 1.2 to 1.8 GHz achieves less than 1 integrated phase error, thus enabling a maximum SNR in excess of 37 dB for VHF and UHF. Multistandard capability is also enabled by programmable channel-select filters. Power consumption is less than 140 mW in DVB-T mode for all three bands.

A 65 nm CMOS Multistandard, Multiband TV Tuner for Mobile and Multimedia Applications

Electrostatic discharge (ESD) protection for high-voltage integrated circuits is challenging due to the requirement of high holding voltage to minimize the risk of ESD-induced latchup and electrical overstress. In this letter, a new silicon-controlled rectifier (SCR) is developed for this particular application. The SCR is designed based on the concept that the holding voltage can be increased by reducing the emitter injection efficiency in the SCR. This is accomplished by using a segmented emitter topology. Experimental data show that the new SCR can possess a holding voltage that is larger than 40 V and a failure current It2 that is higher than 28 mA/mum.

Novel Silicon-Controlled Rectifier (SCR) for High-Voltage Electrostatic Discharge (ESD) Applications

An improved dual-polarity silicon-controlled rectifier (SCR) device has been proposed and realized in a 0.6-mum bipolar complementary metal-oxide-semiconductor process. The device can be used to protect electrostatic discharge (ESD) in both the positive and negative directions on pins with a voltage range that goes below ground. Comparing with the conventional bidirectional SCR structures, the new device is more suitable for low-voltage integrated circuit ESD protection applications because it possesses a smaller trigger voltage, a smaller leakage current, and a larger holding voltage.

An Improved Bidirectional SCR Structure for Low-Triggering ESD Protection Applications

A method for programming one or more reference cells is described. The reference cell is programmed a predetermined amount, its program state is sensed relative to a prescribed cell on the same die (e.g., a memory cell or a golden bit cell), and the programming process continues until the reference cell fails a preselected read operation. In one preferred embodiment, the memory cell used during the reference cell programming process is the cell in the memory array having the highest native threshold value. In another preferred embodiment, the memory cell used during the reference cell programming process is a native cell that is on-board the die containing the memory array, but not a cell within the memory array.

Method for programming a reference cell

This paper presents a new design concept for the control of the holding voltage of LVTSCR ESD protection structures by realizing a negative feedback in the p emitter. The negative feedback is implemented by the creation of a voltage drop using embedded circuit elements. The final clamp voltage is tuned to exceed the power supply level, thus eliminating the potential for latchup. The design is validated by ESD pulse measurements performed on test structures with cascoded, triggered LVTSCRs for 5.5-V tolerant I/O pins in an 0.18-/spl mu/m CMOS process. The results of the first part of the study were used to propose another design for the LVTSCR with a high holding voltage based on emitter area reduction. The proposed device is validated using three-dimensional simulations and experimental analysis.

High holding voltage cascoded LVTSCR structures for 5.5-V tolerant ESD protection clamps

Triggering structures BJT, SCR and bi-directional SCR for high voltage BiCMOS process onchip ESD protection have been developed and analyzed using physical process and device simulation and pulse measurements. A ten-fold increase in the protection levels compared to the reference BJT structures have been demonstrated using a cylindrical lateral SCR and bidirectional SCR.

Comparison of ESD protection capability of lateral BJT, SCR and bidirectional. SCR for hi-voltage BiCMOS circuits

The device level strategy for ESD protection of "free" double diffusion 12 V and 20 V LDMOS devices, realized in a 3.3 V CMOS process, is presented. The self-protection capabilities and limitations of LDMOS devices have been analyzed, along with complementary snapback TFO and SCR devices, under ESD stress conditions. Optimal device type and parameters have been determined.

ESD protection of double-diffusion devices in submicron CMOS processes

An apparatus including an electrostatic discharge (ESD) protection structure with a diac in which substancially similar ESD protection is provided for both positive and negative ESD voltages appearing at the circuit electrode sought to be protected.

Electrostatic discharge (ESD) protection structure with symmetrical positive and negative ESD protection

In a Bi-CMOS ESD protection device, dual voltage capabilities are achieved by providing two laterally spaced p-regions in a n-material and defining a n+ region and a p+ region in each of the p-regions to define I-V characteristics that are similar to those defined by a SCR device in a positive direction, but, in this case, having those characteristics in both directions. The device may be asymmetrical to accommodate different voltage amplitudes in the positive and negative directions.

Ann Concannon

Papers

High holding voltage cascoded LVTSCR structures for 5.5-V tolerant ESD protection clamps

Comparison of ESD protection capability of lateral BJT, SCR and bidirectional. SCR for hi-voltage BiCMOS circuits

ESD protection of double-diffusion devices in submicron CMOS processes

Electrostatic discharge (ESD) protection structure with symmetrical positive and negative ESD protection

Bi-directional ESD protection structure for BiCMOS technology