Showing papers in "IEEE Transactions on Device and Materials Reliability in 2004"

Reliability study of phase-change nonvolatile memories

Abstract: A detailed investigation of the reliability aspects in nonvolatile phase-change memories (PCM) is presented, covering the basic aspects related to high density array NVM, i.e., data retention, endurance, program and read disturbs. The data retention capabilities and the endurance characteristics of single PCM cells are analyzed, showing that data can be stored for 10 years at 110/spl deg/C and that a resistance difference of two order of magnitude between the cell states can be maintained for more than 10/sup 11/ programming cycles. The main mechanisms responsible for instabilities just before failure as well as for final device breakdown are also discussed. Finally, the impact of read and program disturbs are clearly assessed, showing with experimental data and simulated results that the crystallization induced during the cell read out and the thermal cross-talk due to adjacent bits programming do not affect the retention capabilities of the PCM cells.

Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review

Abstract: This paper examines the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications. The review assesses recent proposals to circumvent the SCE in SOI MOSFETs and a short evaluation of strengths and weaknesses specific to each attempt is presented. A new device structure called the dual-material gate (DMG) SOI MOSFET is discussed and its efficacy in suppressing SCEs such as drain-induced barrier lowering (DIBL), channel length modulation and hot-carrier effects, all of which affect the reliability of ultra-small geometry MOSFETs, is assessed.

Flash EEPROM threshold instabilities due to charge trapping during program/erase cycling

Abstract: Charge trapping over the channel can occur from program/erase cycling of Flash memory cells, increasing the cell threshold voltage and causing threshold shifts in retention tests when charges detrap. The empirical characteristics of these effects are discussed. Trapping has a square-root dependence on program/erase cycle count. Detrapping scales with the logarithm of time and is thermally accelerated with an activation energy of 1.1 to 1.2 eV. Detrapping has only a weak dependence on electric field. These mechanisms are intrinsic, yet there is a wide variation in behavior from one cell to another related to Poisson statistical variations. Common reliability characterization methods need to be re-thought in light of the characteristics of this and other mechanisms. In particular, performing extensive program/erase cycling with no delays between cycles is unrealistic for this mechanism, and alternative distributed-cycling schemes are proposed.

Review of cooling technologies for computer products

Abstract: This paper provides a broad review of the cooling technologies for computer products from desktop computers to large servers. For many years cooling technology has played a key role in enabling and facilitating the packaging and performance improvements in each new generation of computers. The role of internal and external thermal resistance in module level cooling is discussed in terms of heat removal from chips and module and examples are cited. The use of air-cooled heat sinks and liquid-cooled cold plates to improve module cooling is addressed. Immersion cooling as a scheme to accommodate high heat flux at the chip level is also discussed. Cooling at the system level is discussed in terms of air, hybrid, liquid, and refrigeration-cooled systems. The growing problem of data center thermal management is also considered. The paper concludes with a discussion of future challenges related to computer cooling technology.

Thermal issues in next-generation integrated circuits

Abstract: The drive for higher performance has led to greater integration and higher clock frequency of microprocessor chips. This translates into higher heat dissipation and, therefore, effective cooling of electronic chips is becoming increasingly important for their reliable performance. We systematically explore the limits for heat removal from a model chip in various configurations. First, the heat removal from a bare chip by pure heat conduction and convection is studied to establish the theoretical limit of heat removal from a bare die bound by an infinite medium. This is followed by an analysis of heat removal from a packaged chip by evaluating the thermal resistance due to individual packaging elements. The analysis results allow us to identify the bottlenecks in the thermal performance of current generation packages, and to motivate lowering of thermal resistance through the board-side for efficient heat removal to meet ever increasing reliability and performance requirements.

Timing vulnerability factors of sequentials

Abstract: Single-event upsets (SEU) from particle strikes have become a key challenge in microprocessor design. Modern superpipelined microprocessors typically contain many thousands of sequentials whose soft-error rate (SER) cannot be neglected any more. An accurate assessment of the SER of sequentials is therefore crucial. This work describes a method for computing timing vulnerability factors (TVFs) of sequentials. Our methology captures the impact of the circuit environment which sequentials are typically placed in. Further, upsets occurring in local clock nodes have been accounted for. Results are presented for master-slave type flip flops and for flow-through latches of a high-performance microprocessor. Our investigations demonstrate that TVFs are a strong function of the propagation delay of the combinational logic and typically vary between /spl sim/0% and 50%. For high-performance microprocessors, we predict average TVF values of the order of 20%-30%. Further, we expect TVFs to be largely technology independent for the same design.

Interface trap generation and hole trapping under NBTI and PBTI in advanced CMOS technology with a 2-nm gate oxide

Abstract: This paper gives an insight into the degradation mechanisms during negative and positive bias temperature instabilities in advanced CMOS technology with a 2-nm gate oxide. We focus on generated interface traps and oxide traps to distinguish their dependencies and effects on usual transistor parameters. negative bias temperature instability (NBTI) and positive bias temperature instability in both NMOS and PMOS have been compared and a possible explanation for all configurations has been suggested. Recovery and temperature effect under NBTI were also investigated showing different behaviors of the two components.

Effects of interface trap generation and annihilation on the data retention characteristics of flash memory cells

Abstract: It is revealed that the interface trap generation rate increases by Fowler-Nordheim current stressing on the tunnel oxide as the channel width of shallow-trench isolation (STI)-isolated NAND flash cells shrinks. Furthermore, we argue that the interface trap annihilation phenomenon during retention mode becomes a major failure mechanism of the data retention characteristics of sub-100-nm cells in addition to the conventional charge loss mechanism. A new interface trap analysis method using the hysteresis of the I/sub d/--V/sub g/ curve is proposed and shows that the interface traps consist of fast traps and slow traps.

Effects of electrical leakage currents on MEMS reliability and performance

Abstract: Electrostatically driven MEMS devices commonly operate with electric fields as high at 10/sup 8/ V/m applied across the dielectric between electrodes. Even with the best mechanical design, the electrical design of these devices has a large impact both on performance (e.g., speed and stability) and on reliability (e.g., corrosion and dielectric or gas breakdown). In this paper, we discuss the reliability and performance implications of leakage currents in the bulk and on the surface of the dielectric insulating the drive (or sense) electrodes from one another. Anodic oxidation of poly-silicon electrodes can occur very rapidly in samples that are not hermetically packaged. The accelerating factors are presented along with an efficient early-warning scheme. The relationship between leakage currents and the accumulation of quasistatic charge in dielectrics are discussed, along with several techniques to mitigate charging and the associated drift in electrostatically actuated or sensed MEMS devices. Two key parameters are shown to be the electrode geometry and the conductivity of the dielectric. Electrical breakdown in submicron gaps is presented as a function of packaging gas and electrode spacing. We discuss the tradeoffs involved in choosing gap geometries and dielectric properties that balance performance and reliability.

Modeling of tunneling current and gate dielectric reliability for nonvolatile memory devices

Abstract: We present a hierarchy of tunneling models suitable for the two- and three-dimensional simulation of logic and nonvolatile semiconductor memory devices. The crucial modeling topics are comprehensively discussed, namely, the modeling of the energy distribution function in the channel to account for hot-carrier tunneling, the calculation of the transmission coefficient of single and layered dielectrics, the influence of quasi-bound states in the inversion layer, the modeling of static and transient defect-assisted tunneling, and the modeling of dielectric degradation and breakdown. We propose a set of models to link the gate leakage to the creation of traps in the dielectric layer, the threshold voltage shift, and eventual dielectric breakdown. The simulation results are compared to commonly used compact models and measurements of logic and nonvolatile memory devices.

Future directions and challenges for ETox flash memory scaling

Abstract: The physical and electrical scaling challenges for ETox/spl trade/ Flash memory, including reliability considerations, will be reviewed with potential directions for solutions identified. As Flash scales into the sub-100-nm regime, challenges arise due to the high voltage/field requirement of the programming and erase mechanisms and the stringent charge storage requirement of the dielectrics. These challenges will be overcome with innovations in new materials, new cell structures, and memory error management. Using these techniques will extend the viability of Flash memory to at least the 45-nm generation.

Performance and reliability features of advanced nonvolatile memories based on discrete traps (silicon nanocrystals, SONOS)

Abstract: In this paper, an overview of today's status and progress, as well as tomorrow's challenges and trends, in the field of advanced nonvolatile memories based on discrete traps is given. In particular, unique features of silicon nanocrystal and SONOS memories will be illustrated through original recent data. The main potentials and main issues of these technologies as candidates to push further the scaling limits of conventional floating-gate Flash devices will be evaluated.

In situ temperature measurement of a notebook computer - a case study in health and usage monitoring of electronics

Abstract: Reliability prediction methods do not generally account for the actual life cycle environment of electronic products, which covers their environmental, operating and usage conditions. Considering thermal loads, thermal management strategies still focus on a design for continuous operation that is often determined based on an accumulation of worst-case assumptions. Health monitoring is a method of assessing the reliability of a product in its actual application conditions. A case study in health and usage monitoring of electronic products is presented for a commercial notebook computer. Internal temperatures were dynamically monitored in situ and statistically analyzed during all phases of the life cycle, including usage, storage, and transportation. The effects of power cycles, usage history, CPU computing resources usage, and external thermal environment on peak transient thermal loads were characterized. Such monitored life cycle temperature data could be applied in a life consumption monitoring methodology, to provide damage estimation and remaining life prediction due to specific failure mechanisms influenced by temperature. These findings could contribute to the design of more sustainable, least-energy consumption thermal management solutions.

Energy efficient thermal management of electronic components using solid-liquid phase change materials

Abstract: Energy efficiency is becoming a key issue in the development of thermal management devices. To this end, thermal performance of plate fin and pin fin heat sinks incorporating a solid-liquid phase change material (PCM) has been evaluated, under periodic power inputs simulating actual heating conditions. Experiments were performed using Wood's metal (50Bi/27Pb/13Sn/10Cd, melting point: 70.0/spl deg/C) under forced convection in a wind tunnel, and also with an integrated fan. A periodic on/off power of 35 W and constant air velocities in the range of 0.5-1.5 m/s were examined. Three different periodic power patterns were utilized. A thermal stabilization period was observed during the phase change from solid to liquid, during which the temperature rise was arrested. The resulting extended operating period, prior to reaching a prescribed maximum temperature, resulted in an improvement in the allowable passive thermal operation time of the heat sinks. The experiments for fan-cooled heat sinks showed that energy savings by using PCM heat sinks were in the range of 5.4-12.4%. Computational predictions were performed using an implicit enthalpy-porosity approach, and were in good agreement with experimental data.

Reliability properties of low-voltage ferroelectric capacitors and memory arrays

Abstract: We report on the reliability properties of ferroelectric capacitors and memory arrays embedded in a 130-nm CMOS logic process with 5LM Cu/FSG. Low voltage (<1.5 V) operation is enabled by the 70-nm thick MOCVD PZT ferroelectric films. Data loss resulting from high temperature bakes is primarily caused by the imprint effect, which shows /spl sim/1.5 eV time-to-fail activation energy. Excellent bit endurance properties are observed on fully packaged memory arrays, with no degradation up to 10/sup 13/ write/read polarization switching cycles. Retention measured after 10/sup 12/ switching cycles demonstrates no degradation relative to arrays with minimal cycling.

Recent developments in thin film adhesion measurement

Abstract: Interfacial fracture energies of thin films may be calculated using many different techniques. Nanoindentation and stressed overlayers are by far the most common and more reliable of the testing techniques. They depend on mechanics-based models to calculate the interfacial fracture energy of an interface using only the site specific material properties and the dimensions of the delaminated region, either in spontaneous buckle or indentation-induced blister form. This study will focus on four adhesion measurement techniques: spontaneous buckles, stressed overlayer-induced buckles, and nanoindentation-induced blisters with and without stressed overlayers, to demonstrate that the techniques will produce similar results for the measurement of adhesion energy. Films of tungsten (W), platinum (Pt), and titanium (Ti) on SiO/sub 2/ (amorphous glass) substrates are examined and values of interfacial fracture energies reported. Results of interfacial fracture energy calculated from spontaneous buckles and indentation-induced blisters compare well to one another and values are reported for the aforementioned films.

Data retention reliability model of NROM nonvolatile memory products

Abstract: Post cycling data retention reliability model of NROM devices is presented. The degradation rate of the threshold voltage of cycled cells is shown to be a multiplication of three functions: 1) bit density; 2) endurance; and 3) storage time and temperature. The functions are fitted to experimental results of products of three technology nodes. The retention loss is interpreted in terms of thermally activated lateral migration of trapped holes in the ONO layer. The holes' migration quenches the electrons' field over the channel of the device, degrading its threshold voltage. The migration process is presented as a dispersive transport process. Saturation of the retention loss is demonstrated at threshold voltage levels well above the neutral state of the device. From the retention loss function we derive a time-to-failure formula and an expression for the thermal acceleration factor of NROM products useful for determining stress conditions for accelerated reliability tests.

Emerging SiGe HBT reliability issues for mixed-signal circuit applications

Abstract: We review the emerging reliability issues associated with high-performance SiGe HBT technologies which are being increasingly deployed in a wide variety of mixed-signal circuit applications. For the purposes of this work, we define the concept of device "reliability" to be broader than its standard usage in the industry, to include all possible transistor degradation mechanisms, for all possible mixed-signal circuit designs, in any of the various intended mixed-signal applications. For instance, in addition to classical device reliability mechanisms associated with reverse emitter-base and high forward current density stress, new reliability issues for SiGe HBTs, including impact-ionization induced "mixed-mode" stress, scaling-induced breakdown voltage compression and operating point instabilities, geometrical scaling-induced low-frequency noise variations, and the impact of ionizing radiation on device and circuit reliability, are also addressed.

Spray cooling using multiple nozzles: visualization and wall heat transfer measurements

Abstract: Time- and space-resolved heat transfer data on a nominally isothermal surface, cooled by two spray nozzles, were obtained using an array of individually controlled microheaters. Visualization and measurements of the liquid-solid contact area and three-phase contact line length were made using a total internal reflectance technique. The spacing between the nozzles and the heated surface was varied between 7 and 17 mm. Little interaction between the two sprays was observed for the tested conditions, with the heat flux due to a single nozzle remaining comparable to that due to two nozzles, provided the areas considered were limited to the regions impacted by the sprays. Variations in the heat transfer across the surface, however, increased significantly with decreasing nozzle-to-heater spacing. The phase change heat transfer was strongly correlated with the length of the three-phase contact line and was not correlated with the wetted area.

High holding voltage cascoded LVTSCR structures for 5.5-V tolerant ESD protection clamps

Abstract: This paper presents a new design concept for the control of the holding voltage of LVTSCR ESD protection structures by realizing a negative feedback in the p emitter. The negative feedback is implemented by the creation of a voltage drop using embedded circuit elements. The final clamp voltage is tuned to exceed the power supply level, thus eliminating the potential for latchup. The design is validated by ESD pulse measurements performed on test structures with cascoded, triggered LVTSCRs for 5.5-V tolerant I/O pins in an 0.18-/spl mu/m CMOS process. The results of the first part of the study were used to propose another design for the LVTSCR with a high holding voltage based on emitter area reduction. The proposed device is validated using three-dimensional simulations and experimental analysis.

Write/erase cycling endurance of memory cells with SiO/sub 2//HfO/sub 2/ tunnel dielectric

Abstract: The write/erase cycling endurance of low voltage floating-gate memory cells programmed and erased by tunneling through a SiO/sub 2//HfO/sub 2/ dual layer tunnel dielectric stack is investigated. The use of fixed single pulse program and erase conditions leads to fast shifting (after /spl sim/1000 cycles) of the threshold voltage window, so that only a limited number of write/erase cycles can be achieved. Increasing the write and erase duration quickly leads to an excessive erase time so that a different erase method has to be used. Improvement of the erase behavior and cycling endurance has been obtained by a combination of two methods. Inclusion of soft write pulses between the erase pulses reduces the amount of charge trapped in the tunnel dielectric and therefore limits the increase in erase time. Also, the erase voltage can progressively be raised in order to further limit the erase time, leading to an endurance of 10 000 cycles on the considered cells. When combining the SiO/sub 2//HfO/sub 2/ stack with channel hot electron injection so that tunneling is only required in one direction, 100 000 write/erase cycles are demonstrated with minimal change of the memory window.

Demonstrated reliability of 4-mb MRAM

Abstract: The successful commercialization of MRAM will rely on providing customers with a robust and reliable memory product. The intrinsic reliability of magnetoresistive tunnel junction (MTJ) memory bits and the metal interconnect system of MRAM are two areas of great interest due to the new materials involved in this emerging technology. Time dependent dielectric breakdown (TDDB) and resistance drift were the two main failure mechanisms identified for intrinsic memory bit reliability. Results indicated that a lifetime over 10 years is achievable under the operating condition. For metal interconnect system, the initial results of Cu with magnetic cladding have met the reliability performance of typical nonclad Cu backend process in electromigration (EM) and iso-thermal annealing (ITA). Finally data retention is demonstrated over times orders of magnitude longer than 10 years.

Reliability and failure analysis of Sn-Ag-Cu solder interconnections for PSGA packages on Ni/Au surface finish

Abstract: The reliability and failure modes of eutectic Sn-Ag-Cu solder joints were studied and compared to eutectic Sn-Pb-Ag ones. Two different failure modes occur: brittle fracture and fatigue. The results show that with a Ni/Au surface finish the reliability of Sn-Ag-Cu solder is much better than that of Sn-Pb-Ag solder. First, when the joint is deformed at high thermomechanical strain, the chance of brittle fracture at the Ni-Au interface is significantly reduced when using Sn-Ag-Cu solder. The reason is a reduced formation of the brittle (Au, Ni)Sn/sub 4/ intermetallic at the UBM interface, responsible for the brittle fracture mode. Second, after deformation at low thermomechanical strain, both solders fail due to solder fatigue, but the Sn-Ag-Cu shows a better lifetime. This better reliability of the Sn-Ag-Cu solder is attributed to a new solder fatigue mechanism: the crack propagates through the bulk of the solder in a web-fashion way, linking the Au-containing particles formed in the volume. This is beneficial for the joint reliability as it hinders the crack propagation.

Environmental effects on cracking and delamination of dielectric films

Abstract: The effects of temperature and moisture on the adhesive and cohesive strength of dielectric materials and the interfaces that are composed of those materials commonly found in thin-film interconnect structures are reviewed. Debond growth rate versus debond driving energy curves (V-G curves) were collected over a range of environmental conditions for both dielectrics and dielectric/metal interfaces. Both are found to exhibit characteristics consistent with stress corrosion cracking mechanisms found in the bulk glass literature. The mechanisms identified in both systems are explained in terms of the salient chemical reactions occurring at the debond tip.

Evaluation of SiO/sub 2/ antifuse in a 3D-OTP memory

Abstract: We have evaluated an antifuse technology used in a novel three-dimensional one-time-programmable (3D-OTP) nonvolatile solid-state memory. The 3D-OTP memory uses deposited polysilicon antifuse sandwiches to build its memory cells. The polysilicon based SiO/sub 2/ antifuse show different breakdown characteristics compared to conventional traditional gate oxides. Long-term storage tests show that this 3D-OTP solid-state memory not only can be a general purpose ROM, but also can be an ideal media for archiving.

Mechanics of thin films and microdevices

Abstract: This paper discusses the latest developments in nanomechanics of thin films with applications in microelectromechanical systems (MEMS) and microelectronics. A precise methodology that combines in situ atomic force microscopy (AFM) surface measurements of uniaxially tension-loaded MEMS specimens and strain analysis via digital image correlation (DIC) achieving 0.1 pixel spatial displacement resolution is presented. By this method, the mechanical deformation of thin films was obtained in areas as small as 4 /spl times/ 4 /spl mu/m and with 1-2 nm spatial displacement resolution supporting the derivation of interrelations between the material microstructure and the local mechanical properties. This methodology provided for the first time the values of Young's modulus and Poisson's ratio from specimens with cross-sections as small as 2 /spl times/ 6 /spl mu/m. The value of properties derived via AFM/DIC demonstrated very limited scatter compared to indirect mechanical property measurement methods. The application of this technique on nonuniform geometries resolved nanoscale displacement and strain fields in the vicinity of ultrasharp elliptical perforations achieving very good agreement with finite element models. Furthermore, the stochastic and deterministic material failure properties described via Weibull statistics and fracture toughness, respectively, are illustrated for brittle thin films. Failure initiated at notches was found to be influenced by the local radius of curvature and the stress concentration factor. Precise fracture toughness values for MEMS materials were obtained from MEMS specimens with atomically sharp cracks. These studies were supported by measurements of displacements/strains conducted for the first time in the vicinity of mathematically sharp cracks via the AFM/DIC method. The method can be applied to a variety of thermomechanical reliability problems in multilayered thin films and inhomogeneous/anisotropic materials.

A review of ionizing radiation effects in floating gate memories

Abstract: The effects of ionizing radiation on microelectronics are traditionally a concern for devices intended for the space use, but they are becoming important even at ground level. Ionizing radiation effects can be broadly divided in two classes: total ionizing dose (progressive buildup of defects) and single event effects (macroscopic result of a single microscopic event). In both cases, ionizing radiation can lead to severe degradation of device performance, possibly resulting in device failure. This work is a review of literature results concerning both classes of ionizing radiation-related phenomena on floating gate memories. Regardless of its nature, ionizing radiation impacts two aspects of the performance and reliability of floating gate memories: the functionality and the adherence to specifications of the control circuitry, and the degradation of stored information in the array itself.

Interlevel dielectric failures in copper/low-k structures

Abstract: Failure modes for inter-level dielectric layers under accelerated test conditions have been evaluated for a range of dielectric diffusion barriers in copper/low-k structures. The dominant failure mechanism for both constant voltage tests and ramped voltage tests was mechanical cracking at the dielectric barrier/low-k interface. Few occurrences of copper diffusion through the bulk ILD were observed. A simple model for the dominant failure mechanism is proposed which hypothesizes crack formation due to the electrostatic force between interdigitated lines followed by copper extrusion into the cracks. The proposed model is consistent with measurements of interfacial adhesion strengths in Cu/low-k stacks.

CMOS RF and DC reliability subject to hot carrier stress and oxide soft breakdown

Abstract: Hot carrier and soft breakdown effects are evaluated experimentally. A methodology to systematically study hot carrier and soft breakdown effects on RF circuits is developed. Device stress measurement and SpectreRF simulation are conducted to evaluate the impact of hot carrier and soft breakdown effects on RF circuits such as low-noise amplifier and voltage-controlled oscillator performances. Two design techniques to build reliable RF circuits are proposed.

Off-state breakdown of GaAs PHEMTs: review and new data

Abstract: This paper reviews the literature dealing with off-state gate-drain breakdown in MESFET and HEMT structures, with particular emphasis on GaAs PHEMTs, in terms of: 1) the physics of the breakdown phenomenon; 2) the breakdown walkout effect; 3) the impact of design and process choices on the breakdown behavior; and 4) the experimental techniques used for breakdown characterization. A thorough temperature-dependent breakdown characterization of commercial PHEMTs is also shown and discussed. It is found that different physical mechanisms may dominate the gate-drain leakage depending on the reverse bias and temperature range considered, and the particular PHEMT technology. The main results shown here tell us the following. 1) The breakdown voltages are decreasing functions of temperature between room temperature and 160/spl deg/C. 2) Between room temperature and 90-100/spl deg/C, thermionic-field emission seems be dominant, with low activation energies below 0.15 eV; as a consequence, the temperature dependence of the breakdown voltage is weak. 3) Between 110/spl deg/C and 160/spl deg/C, higher activation energy mechanisms (possibly trap-assisted tunneling and thermionic emission over a field-dependent barrier) tend to dominate, and the temperature dependence of the breakdown voltages is stronger.