A
Anthony-Trung D. Nguyen
Researcher at Intel
Publications - 12
Citations - 467
Anthony-Trung D. Nguyen is an academic researcher from Intel. The author has contributed to research in topics: Cache & Crowd simulation. The author has an hindex of 7, co-authored 12 publications receiving 438 citations.
Papers
More filters
Journal ArticleDOI
Second Life and the New Generation of Virtual Worlds
Sanjeev Kumar,Jatin Chhugani,Changkyu Kim,Daehyun Kim,Anthony-Trung D. Nguyen,Pradeep Dubey,Christian Bienia,Youngmin Kim +7 more
TL;DR: An analysis of Second Life illustrates the demands metaverses applications place on clients, servers, and the network and suggests possible optimizations.
Journal ArticleDOI
Convergence of Recognition, Mining, and Synthesis Workloads and Its Implications
Yen-Kuang Chen,Jatin Chhugani,Pradeep Dubey,Christopher J. Hughes,Daehyun Kim,Sanjeev Kumar,Victor W. Lee,Anthony-Trung D. Nguyen,Mikhail Smelyanskiy +8 more
TL;DR: A diverse set of emerging RMS applications from market segments like graphics, gaming, media-mining, unstructured information management, financial analytics, and interactive virtual communities presents a relatively focused, highly overlapping set of common platform challenges.
Journal ArticleDOI
Mapping High-Fidelity Volume Rendering for Medical Imaging to CPU, GPU and Many-Core Architectures
Mikhail Smelyanskiy,David R. Holmes,Jatin Chhugani,A. Larson,Doug Carmean,Dennis P. Hanson,Pradeep Dubey,Kurt E. Augustine,Daehyun Kim,A. Kyker,Victor W. Lee,Anthony-Trung D. Nguyen,Lauren H. Seiler,Richard A. Robb +13 more
TL;DR: This work describes a thread- and data-parallel implementation of ray-casting that makes it amenable to key architectural trends of three modern commodity parallel architectures: multi-core, GPU, and an upcoming many-core Intelreg architecture code-named Larrabee.
Patent
System and method for memory bandwidth friendly sorting on multi-core architectures
Jatin Chhugani,Sanjeev Kumar,Anthony-Trung D. Nguyen,Yen-Kuang Chen,Victor W. Lee,William W. Macy +5 more
TL;DR: In this article, a tree merge sort is performed on the nodes that are cache resident until a block of data migrates to a root node, and the completed output list in memory storage is a list of the fully sorted data.
Patent
Virtual row buffers for use with random access memory
Changkyu Kim,Albert Lin,Christopher J. Hughes,Anthony-Trung D. Nguyen,Yen-Kuang Chen,Zeshan A. Chishti,Bryan K. Casper +6 more
TL;DR: In this article, the authors proposed a method to reduce the energy consumption of a memory chip while increasing its effect bandwidth during the execution of any workload by using virtual row buffers to respond to requests for data included in memory array blocks.