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Arturo Hernández Aguirre
Researcher at Tulane University
Publications - 54
Citations - 1149
Arturo Hernández Aguirre is an academic researcher from Tulane University. The author has contributed to research in topics: Evolutionary algorithm & Multi-objective optimization. The author has an hindex of 17, co-authored 53 publications receiving 1102 citations. Previous affiliations of Arturo Hernández Aguirre include Consejo Nacional de Ciencia y Tecnología & Universidad Autónoma Metropolitana.
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Journal ArticleDOI
Handling constraints using multiobjective optimization concepts
Arturo Hernández Aguirre,Salvador Botello Rionda,Carlos A. Coello Coello,Giovanni Lizárraga,Efrén Mezura Montes +4 more
TL;DR: In inverted‐shrinkable PAES, this approach combines the use of multiobjective optimization concepts with a mechanism that focuses the search effort onto specific areas of the feasible region by shrinking the constrained search space.
Journal ArticleDOI
Evolutionary multi-objective optimization
TL;DR: A reference-point-based many-objective evolutionary algorithm following NSGA-II framework (NSGA-III) that emphasizes population members that are non-dominated, yet close to a set of supplied reference points is suggested.
Proceedings ArticleDOI
Constrained optimization via particle evolutionary swarm optimization algorithm (PESO)
TL;DR: This work introduces the PESO (Particle Evolutionary Swarm Optimization) algorithm for solving single objective constrained optimization problems and proposes two new perturbation operators: "c-perturbation" and "m-perturbedation".
Book ChapterDOI
Use of particle swarm optimization to design combinational logic circuits
TL;DR: Results indicate that particle swarm optimization may be a viable alternative to design combinational circuits at the gate-level.
Journal ArticleDOI
Design of combinational logic circuits through an evolutionary multiobjective optimization approach
TL;DR: The results indicate that the proposed approach can significantly reduce the computational effort required by a genetic algorithm to design circuits at a gate level while generating equivalent or even better solutions than a human designer or even other GAs.