This paper presents an overview of technical challenges in achieving higher integration levels, lower power dissipation, smaller form factor, and lower cost in portable battery-powered RF transceivers for personal communications applications. Specific emphasis is placed on silicon integrated circuits for transceivers in the 800 MHz-2.5 GHz range of frequencies.

Future directions in silicon ICs for RF personal communications

The invention provides a single chip implementation of a digital receiver for multicarrier signals that are transmitted by orthogonal frequency division multiplexing. Improved channel estimation and correction circuitry are provided. The receiver has highly accurate sampling rate control and frequecy control circuitry. BCH decoding of tps data carriers is achieved with minimal resources with an arrangement that includes a small Galois field multiplier. An improved FFT window synchronization circuit is coupled to the resampling circuit for locating the boundary of the guard interval transmitted with the active frame of the signal. A real-time pipelined FFT processor is operationally associated with the FFT window synchronization circuit and operates with reduced memory requirements.

Single chip VLSI implementation of a digital receiver employing orthogonal frequency division multiplexing

A CMOS integrated signal processing system for a sampling receiver includes a timing recovery circuit, wherein an on-chip numerically controlled oscillator is operative at periods T that are initially equal to the nominal baud rate of the signals controls a sinc interpolator receiving samples at the sampling rate. A loop filter is coupled to the sinc interpolator and to the numerically controlled oscillator. The arrangement is capable of handling various symbol rates. The system includes a circuit for carrier recovery, having a second on-chip numerically controlled oscillator, a digital derotation circuit responsive to the second numerically controlled oscillator, accepting an in phase component and a quadrature component of the sampled signals. An adaptive phase error estimation circuit is coupled in a feedback loop.

Signal processing system

A 200 MHz quadrature direct digital frequency synthesizer/complex mixer (QDDFSM) chip is presented. The chip synthesizes 12 b sine and cosine waveforms with a spectral purity of -84.3 dBc. The frequency resolution is 0.047 Hz with a corresponding switching speed of 5 ns and a tuning latency of 14 clock cycles. The chip is also capable of frequency, phase, and quadrature amplitude modulation. These modulation capabilities operate up to the maximum clocking frequency. The chip provides the capability of parallel operation of multiple chips with throughputs up to 800 MHz. The 0.8 /spl mu/m triple level metal N-well CMOS chip has a complexity of 52000 transistors with a core area of 2.6/spl times/6.1 mm/sup 2/. Power dissipation is 2 W at 200 MHz and 5 V. >

A 200 MHz quadrature digital synthesizer/mixer in 0.8 /spl mu/m CMOS

A method and apparatus are disclosed for determining the boundaries of guard intervals of data symbols being received in a coded orthogonal frequency division multiplexed signal. Temporal samples separated by an interval of an active interval of a data symbol are associated in pairs, and difference signals obtained. The dispersion of a first comparison block of difference signals is determined, and compared to the dispersion of a second comparison block of difference signals, the second comparison block being displaced from the first comparison block by n samples. An F ratio is calculated for the dispersions of the two blocks. F ratios are iterated in a succession of comparison blocks, and a signal representing the F ratios subjected to peak detection. The peaks represent the boundaries of the symbol's guard interval. This information is utilized in synchronizing an FFT window for subsequent signal reconstruction.

Timing synchronization in a receiver employing orthogonal frequency division multiplexing

A 200-MHz universal all-digital quadrature modulator and demodulator are presented for implementing the front-end signal processing functions for high-bit-rate digital radio applications. The modulator chip accepts a pair of 8-b in-phase and quadrature data streams and generates a band-limited IF digital output. The demodulator chip accepts a digitized IF input signal and generates a pair of filtered in-phase and quadrature baseband signals. The modulator and demodulator chips each incorporate matched 40-tap finite-impulse-response (FIR) square-root Nyquist filters and can accommodate symbol rates up to Mbd. The modulator chip can generate any arbitrary signal constellation within a rectangular grid of 256*256 points, thus resulting in a generic chip set suitable for a wide variety of high-bit-rate digital modem designs using various advanced multilevel modulation formats such as M-ary QAM. Both chips were fabricated in a 1.2- mu m CMOS process. >

B.C. Wong

Papers

A 200-MHz all-digital QAM modulator and demodulator in 1.2- mu m CMOS for digital radio applications