Journal ArticleDOI
A 200-MHz all-digital QAM modulator and demodulator in 1.2- mu m CMOS for digital radio applications
B.C. Wong,Henry Samueli +1 more
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TLDR
A 200-MHz universal all-digital quadrature modulator and demodulator are presented for implementing the front-end signal processing functions for high-bit-rate digital radio applications.Abstract:
A 200-MHz universal all-digital quadrature modulator and demodulator are presented for implementing the front-end signal processing functions for high-bit-rate digital radio applications. The modulator chip accepts a pair of 8-b in-phase and quadrature data streams and generates a band-limited IF digital output. The demodulator chip accepts a digitized IF input signal and generates a pair of filtered in-phase and quadrature baseband signals. The modulator and demodulator chips each incorporate matched 40-tap finite-impulse-response (FIR) square-root Nyquist filters and can accommodate symbol rates up to Mbd. The modulator chip can generate any arbitrary signal constellation within a rectangular grid of 256*256 points, thus resulting in a generic chip set suitable for a wide variety of high-bit-rate digital modem designs using various advanced multilevel modulation formats such as M-ary QAM. Both chips were fabricated in a 1.2- mu m CMOS process. >read more
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Proceedings ArticleDOI
Future directions in silicon ICs for RF personal communications
Paul R. Gray,Robert G. Meyer +1 more
TL;DR: In this article, the authors present an overview of technical challenges in achieving higher integration levels, lower power dissipation, smaller form factor, and lower cost in portable battery-powered RF transceivers for personal communications applications.
Patent
Single chip VLSI implementation of a digital receiver employing orthogonal frequency division multiplexing
Peter Anthony Keevill,Dawood Alam,John Matthew Nolan,Matthew James Collins,Thomas Foxcroft,David Huw Davies,Jonathan Parker +6 more
TL;DR: In this paper, a single chip implementation of a digital receiver for multicarrier signals that are transmitted by orthogonal frequency division multiplexing is presented, which has highly accurate sampling rate control and frequecy control circuitry.
Patent
Signal processing system
TL;DR: A CMOS integrated signal processing system for a sampling receiver includes a timing recovery circuit, wherein an on-chip numerically controlled oscillator is operative at periods T that are initially equal to the nominal baud rate of the signals controls a sinc interpolator receiving samples at the sampling rate.
Journal ArticleDOI
A 200 MHz quadrature digital synthesizer/mixer in 0.8 /spl mu/m CMOS
Loke Kun Tan,Henry Samueli +1 more
TL;DR: A 200 MHz quadrature direct digital frequency synthesizer/complex mixer (QDDFSM) chip is presented in this article with a spectral purity of -84.3 dBc and frequency resolution is 0.047 Hz with a corresponding switching speed of 5 ns and a tuning latency of 14 clock cycles.
Patent
Timing synchronization in a receiver employing orthogonal frequency division multiplexing
TL;DR: In this paper, a method and apparatus for determining the boundaries of guard intervals of data symbols being received in a coded orthogonal frequency division multiplexed signal is described, where temporal samples separated by an interval of an active interval of a data symbol are associated in pairs and difference signals obtained.
References
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High-speed CMOS circuit technique
Jiren Yuan,Christer Svensson +1 more
TL;DR: It is shown that clock frequencies in excess of 200 MHz are feasible in a 3- mu m CMOS process, and a precharge technique with a true single-phase clock, which increases the clock frequency and reduces the skew problems, is used.
Journal ArticleDOI
NORA: a racefree dynamic CMOS technique for pipelined logic structures
N.F. Goncalves,H. De Man +1 more
TL;DR: A new dynamic CMOS technique which is fully racefree, yet has high logic flexibility, and logic inversion is provided, which means higher logic flexibility and less transistors for the same function.
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A true single-phase-clock dynamic CMOS circuit technique
TL;DR: The authors describe two dynamic circuit techniques, using only a single-phase clock which is never inverted, which has the advantages of simple clock distribution, small area for clock lines reduced clock skew problems, and high speed.
Journal ArticleDOI
A 15-ns 32*32-b CMOS multiplier with an improved parallel structure
TL;DR: In this paper, a high-speed 32*32b parallel multiplier with an improved parallel structure using 0.8-mu m CMOS triple-level-metal technology is discussed.
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