This paper presents a novel 3D structured ASIC platform that lowers the development effort required to deploy 3D integration technologies in cost sensitive, low-volume applications. The key advantage of this structured 3D ASIC architecture, over custom 3D ASICs, is a fixed vertical interconnect pattern that is programmed by a single 2D metal-via mask, allowing individual die levels to be rapidly designed, fabricated, and assembled. The first silicon realization of this architecture is a 3D-stackable 12×12mm structured ASIC die with 42K interconnects, which is resource compatible with an existing 2D structured ASIC device of the same size. 3D die stacks built using this platform are also intended to be a less costly and more flexible replacement for a large 20×20mm monolithically integrated structured ASIC device. This 3D structured ASIC platform was des igned and fabricated in Sandia's 0.35-μm foundry, and high-density front-end-of-line through silicon vias (TSVs) were developed to implement the 3D vertical interconnects1.

A quick-turn 3D structured ASIC platform for cost-sensitive applications

As integrated circuit dimensions scale downward the costs of the photolithographic masks used to manufacture microcircuits are becoming prohibitively high. And in today's highly competitive business environment, time to market is increasingly critical. Custom standard-cell ASICs are on the wrong side of these dynamics with their long lead times and the need to build a full mask set per part number. Structured ASICs offer an attractive alternative. Structured ASICs are developed from an inventoried base masterslice chip design by using generally only a few back-end masking levels to personalize the resulting ASIC function, saving mask costs and shortening lead times per circuit design. Structured ASICs strategically fill the trade space between FPGAs and custom ASICs. BAE Systems has developed a radiation hardened structured ASIC product offering for next-generation advanced military and space applications

B. Orlowsky

Papers

Structured ASIC Design for Space Systems Applications