We propose in this letter a new passivation method to get rid of parasitic surface conduction in oxidized high resistivity (HR) silicon and HR silicon-on-insulator (SOI) wafers. The method consists in passivating the HR substrate with a rapid thermal anneal (RTA)-crystallized layer of silicon. The electrical efficiency of this new passivation technique is analyzed and shown to be superior over previously published methods. The surface roughness as well as the stability over temperature of this layer are also investigated. It is shown that this new passivation method is the only one simultaneously combining a low surface roughness and a high stability over long thermal anneals. In the context of SOI technology, it therefore appears as the most suitable technique for the substrate passivation of HR SOI wafers, for which a bonding between an oxidized silicon wafer and a passivated HR substrate is required.

New substrate passivation method dedicated to HR SOI wafer fabrication with increased substrate resistivity

Surface passivation of high-resistivity silicon (HRS) by amorphous silicon thin-film deposition is demonstrated as a novel technique for establishing HRS as a microwave substrate. Metal-oxide-silicon (MOS) capacitor measurements are used to characterize the silicon surface properties. An increase of the quality factor (Q) of a 10-nH spiral inductor by 40% to Q=15 and a 6.5-dB lower attenuation of a coplanar waveguide (CPW) at 17 GHz indicate the beneficial effect of the surface passivation for radio frequency (RF) and microwave applications. Regarding CPW attenuation, a nonpassivated 3000-/spl Omega//spl middot/cm substrate is equivalent to a 70-/spl Omega//spl middot/cm passivated substrate. Surface-passivated HRS, having minimum losses, a high permittivity, and a high thermal conductivity, qualifies as a close-to-ideal radio frequency and microwave substrate.

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Surface-passivated high-resistivity silicon substrates for RFICs

An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer.

Trap rich layer for semiconductor devices

We introduce in this work a new quality factor called effective resistivity (rho(eff)), which is used to characterize and fairly compare the substrate resistivity of fully processed SOI wafers. The impacts on rho(eff) (and thus on microwave losses) of the bias (V-a), fixed oxide charges (Q(ox)) traps at the SiO2/Si interface (D-it), oxide thickness (t(ox)) and line geometry are quantified and discussed for the first time. Different design and technological conclusions are drawn. (C) 2004 Elsevier Ltd. All rights reserved.

Effective resistivity of fully-processed SOI substrates

In this paper, we investigate the impact of a passivation layer on the performance of a commercial high-resistivity (HR) SOI CMOS technology. The passivation layer consists of a 300-nm-thick polysilicon cover located directly below the buried oxide (BOX). Both passive and active devices are studied. It is demonstrated that substrate passivation completely suppresses substrate losses that are usually induced by parasitic surface conduction at the substrate/BOX interface in oxidized HR Si substrates. We also report no effect of the underlying polysilicon on the dc and RF behavior of MOSFETs devices. The results shown here strongly suggest that substrate passivation using polysilicon is a promising tool to eradicate substrate losses in HR SOI wafers, thereby increasing the performance of functional SOI logic and high-speed circuits.

RF Performance of a Commercial SOI Technology Transferred Onto a Passivated HR Silicon Substrate

This work reports on an investigation of capacitance-voltage (C-V) measurement of metal-oxide-semiconductor (MOS) capacitors on high resistivity silicon (HRS) used as substrate for radio-frequency (RF) integrated circuits. C-V MOS-capacitor characteristics differ considerably from those on low-resistivity silicon (LRS) due to potential drop in the substrate and large Debye length. Modeling of the substrate by a simple network of parallel resistors and capacitors is found to be insufficient at high frequencies in HRS. Medici simulations confirm the conclusions.

B. Rong

Papers

Surface-passivated high-resistivity silicon substrates for RFICs

C-V characterization of MOS capacitors on high resistivity silicon substrate